Signal integrity is the backbone of successful PCB designs. EP-Scan offers a user-friendly interface that streamlines your PCB design journey. With EP-Scan, you can:
Adjust stack up properties: Understand the impact of substrate stack-up properties on performance
Check against specifications: Apply specifications on impedance, return loss, and insertion loss to see a pass/fail evaluation
Identify layout issues: Spot potential concerns like via stubs and return path discontinuities
Create analysis report: Generate a report with simulation results and pass/fail status with one click
Simplify design version simulation: Streamline simulation on revisions by eliminating setup time with the test plan feature.
Will your DDR Trace Impedance Pass the Specification?
This demo uses EP-Scan to import the ODB++ (design for manufacturing format) and examine the DDR impedance values of an open-source board. After importing the ODB++ layout and configuring the substrate stack-up, it takes only 3 steps to verify whether the impedance of the nets passes the specification. The steps are:
Select the nets
Assign the nets and the 50-Ohm specification to a test plan
Run the test plan
After the simulation is done, a simulation report is just one click away.
PathWave EP-Scan 2024 includes the following new features and major enhancements:
Improved visualization: See your board layout and nets in a 2D viewer
Eye diagram generation: Provide a straightforward view of your signal integrity
Components included in the simulation: Configure and analyze the nets connected by components
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