With ever-increasing device switching speeds comes the challenge of maintaining the integrity of the signal, and meeting the signal’s timing requirements. The timing requirements are met by matching the routed lengths of the signal paths. For a set of 2-pin signal paths, each running from an output pin to a single input pin, calculating and comparing the lengths is a straightforward process. This is not the case for many typical design solutions though where there may be a series termination component in the signal path, or there are more than two pins in the signal, which could then be routed using a Balanced T or a Fly-By routing topology.
In this webinar, you’ll learn about:
What are the Challenges & Solutions in high speed design
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