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Capabilities · FPGA Verification

FPGA verification, from the first lint to a running board.

Questa FPGA Essentials from Siemens EDA, supplied and supported in India by GSAS, and the engineers to set up lint, write UVM testbenches and bring the design up on a prototyping board.

Talk to a verification engineerWhat we verify
  1. 01 What we verify
  2. 02 How we work
  3. 03 The tools
01 What we verify

FPGA verification tools and services in India, as one flow.

The simulator, the checks around it and the board after it, organised by what a verification team needs. Each card lights its place in the flow.

An FPGA verification flow: lint, a UVM testbench on Questa around the design, coverage, and a prototyping board, numbered as on the cards QUESTA ONE FAMILY formal · CDC · wider coverage, same testbenches RTL lint UVM ENVIRONMENT · QUESTA DUT agent sequencer driver monitor score board cover bitstream PROTOTYPE · FPGA BOARD FPGA 1. Lint gate: RTL checked before the first simulation 1 2. Simulator: Questa running the design under test 2 3. Stimulus: Sequencer and driver, constrained-random 3 4. Checking: Monitor and scoreboard 4 5. Coverage: Functional coverage model 5 6. Prototype: The design running on an FPGA board 6 7. Formal and CDC: Wider analyses in the Questa One family 7
  • 1. Lint gate: RTL checked before the first simulation
  • 2. Simulator: Questa running the design under test
  • 3. Stimulus: Sequencer and driver, constrained-random
  • 4. Checking: Monitor and scoreboard
  • 5. Coverage: Functional coverage model
  • 6. Prototype: The design running on an FPGA board
  • 7. Formal and CDC: Wider analyses in the Questa One family
Hover, tap or focus a card or a numbered point to see where it sits in the flow.
  1. 01

    Questa FPGA Essentials

    The Siemens EDA FPGA simulator, the tool many teams still call QuestaSim.

    • VHDL, Verilog, SystemVerilog and mixed-language
    • Off-line waveform debug and root-cause analysis
    • Libraries for AMD/Xilinx, Intel, Lattice, Microchip

    Siemens EDA · Supplied in India by GSAS

  2. 02

    RTL lint and code quality

    Catch the bug at the source, before it costs a simulation run.

    • Undriven signals, width mismatches, combinational loops
    • Synthesis-simulation mismatch rules
    • Lint gates in CI pipelines

    Questa Core + Lint

  3. 03

    UVM testbench development

    Reusable testbenches that carry forward if the design moves to ASIC.

    • Testbench architecture for coverage-driven verification
    • Constrained-random stimulus and scoreboards
    • Functional coverage models

    UVM · SystemVerilog

  4. 04

    Prototyping on hardware

    Validate in simulation, then run the same design on real silicon.

    • Digilent Zynq and Artix-7 boards
    • Arm MPS3 for Cortex-M IP evaluation
    • Questa-to-Vivado simulation library setup

    Digilent · Arm · Vivado · Quartus

  5. 05

    Growing into Questa One

    When designs outgrow simulation and lint, the testbenches come along.

    • CDC methodology for multi-clock designs
    • Formal verification introduction and rollout
    • Existing testbenches, scripts and IP carried forward

    Questa One family

02 How we work

Catch each bug at the cheapest point it can be caught.

Lint finds coding errors before they cost a simulation run, simulation and coverage find behaviour bugs before they reach hardware, and the board proves the design at speed. Hover a stage to see its part of the flow.

Lint · Simulate · Prototype
  1. 01 RTL Source
  2. 02 Lint Rule sets
  3. 03 CI gate Every change
  4. 04 Testbench UVM
  5. 05 Stimulus Constrained-random
  6. 06 Scoreboard Checking
  7. 07 Coverage Closure
  8. 08 Debug Waveforms
  9. 09 Bitstream Vivado · Quartus
  10. 10 Board Prototype

  1. 01

    Lint

    Rules
    rule sets configured and customised
    Catches
    undriven signals, width mismatches, loops
    Also
    incomplete sensitivity lists, sim-synth mismatch
    Gate
    lint in the CI pipeline, style enforced

    Questa Core + Lint bundle

  2. 02

    Simulate

    Languages
    VHDL, Verilog, SystemVerilog, mixed
    Methodology
    UVM, constrained-random stimulus
    Checking
    scoreboards, coverage models
    Debug
    off-line waveform and root-cause analysis

    Pre-configured FPGA vendor libraries

  3. 03

    Prototype

    Boards
    Digilent Zynq-7000, Zynq UltraScale+, Artix-7
    Arm IP
    MPS3 for Cortex-M evaluation
    Libraries
    Questa-to-Vivado simulation setup
    Toolchains
    Vivado and Quartus

    Boards supplied by GSAS in India

03 The tools

Looking for QuestaSim? This is what it is called now.

The simulator has changed names more than once. Questa FPGA Essentials is the FPGA bundle GSAS supplies in India, and it belongs to the Siemens EDA Questa One family.

  1. ModelSim

    The simulator many FPGA teams learned on. Its URL now redirects to Questa One Sim.

  2. QuestaSim

    The name most engineers in India still search for.

  3. Questa FPGA Essentials

    The FPGA bundle GSAS supplies: Questa Core, or Questa Core + Lint.

  4. Questa One

    The Siemens EDA verification family the simulator now belongs to.

Bundle

Questa Core

  • Mixed-language simulation
  • UVM support
  • Waveform debug
  • FPGA vendor libraries

Bundle

Questa Core + Lint

  • Everything in Questa Core
  • RTL lint analysis
  • Synthesis and style checks
  • Findings before simulation

Pre-configured vendor libraries

  • AMD/Xilinx
  • Intel/Altera
  • Lattice
  • Microchip
Questa FPGA Essentials in detail →

The simulator and the boards after it

04 Working together

Three ways to start, depending on what you need.

The tool on its own, a move from ModelSim, or engineers to build the verification environment with you.

  1. 01

    Buy and set up Questa

    Licensing in India

    Questa FPGA Essentials supplied by an authorised Siemens EDA engineering partner, with INR invoicing, GST-compliant documentation and application engineering on your own designs.

    Request a quote

  2. 02

    Move off ModelSim

    Migration

    A migration path for teams on ModelSim or Questa Base, so existing scripts and testbenches carry forward. GSAS engineers can benchmark it against your current simulator on your designs.

    Talk to an engineer

  3. 03

    Build the testbench with us

    UVM and training

    GSAS engineers design the UVM architecture for your design, write the stimulus, coverage models and scoreboards, and train your verification team, including on-site workshops.

    FPGA design services
05 Contact

Evaluating FPGA verification tools?

Tell us your devices, your current simulator and where the bugs are getting through. GSAS replies with a configuration and a quote, and can benchmark Questa FPGA Essentials on your own designs.

Discuss your projectBook a demo

sales@gsasindia.com +91 80 6590 1783

Questions

FPGA verification tools in India

Is Questa FPGA Essentials the same as QuestaSim?

Questa FPGA Essentials is the Siemens EDA FPGA bundle built on the Questa simulator, the tool historically sold as QuestaSim and, before that, ModelSim. Siemens has since brought its verification line under the Questa One brand. Teams looking for QuestaSim for FPGA work should look at Questa FPGA Essentials.

Does Questa FPGA Essentials support UVM?

Yes. It supports the Universal Verification Methodology alongside SystemVerilog, VHDL, Verilog and mixed-language simulation, so a testbench built for an FPGA carries forward if the design later moves to ASIC.

What is the difference between Questa Core and Questa Core + Lint?

Questa Core is the simulator with UVM support, waveform debug and FPGA vendor libraries. Questa Core + Lint adds RTL lint analysis that flags coding errors, synthesis-simulation mismatches, undriven signals and style violations before simulation begins.

Can we move from ModelSim without rewriting our scripts?

Questa FPGA Essentials has a migration path for teams on ModelSim or Questa Base, so existing scripts and testbenches carry forward. GSAS engineers can benchmark it against your current simulator on your own designs.

Can GSAS write the UVM testbench for us?

Yes. GSAS engineers design UVM testbench architecture for your design, implement constrained-random stimulus, coverage models and scoreboards, and train your verification team on the methodology, including on-site workshops.

Can we buy Questa FPGA Essentials in India?

Yes. GSAS Micro Systems is an authorised Siemens EDA engineering partner in India and supplies Questa FPGA Essentials with INR invoicing, GST-compliant documentation and local application engineering from Bengaluru, Hyderabad, Chennai, Pune, Mumbai and Delhi NCR.