01
RTL design
Digital design from specification to synthesis-ready RTL.
- Custom IP cores and configurable modules
- Bus interfaces: AXI, APB, AHB
- Protocol controllers and DSP pipelines
VHDL · SystemVerilog
Capabilities · FPGA Design
FPGA design, from RTL to a timing-closed, working board.
RTL in VHDL and SystemVerilog, UVM verification, synthesis and timing closure, and processor-to-fabric integration on Zynq and Versal, from an engineering team in Bengaluru that verifies what it designs.
01 What we design
Five kinds of FPGA work, and where each lands on the chip.
Organised by what a project needs done, from a single IP block to a full processor-plus-fabric system. Each card lights its part of the SoC.
- 1. Custom IP: RTL blocks and protocol controllers in the fabric
- 2. AXI interconnect: AXI, APB and AHB bus interfaces
- 3. DSP pipeline: Signal-processing datapaths in the fabric
- 4. Clocking: Clock trees, constraints and timing closure
- 5. Processing system: Arm cores running PetaLinux or bare-metal code
- 6. DMA and memory: DMA engines between fabric and DDR
- 7. High-speed I/O: Real-world interfaces at the device pins
- 8. Clock-domain crossing: CDC and RDC analysis between clock domains
-
- 02
Verification and UVM
Testbenches written alongside the design, not after it.
- Constrained-random UVM testbenches
- Coverage-driven and assertion-based verification
- CDC and RDC analysis, formal property checking
UVM · Coverage · Assertions
- 03
Synthesis and timing closure
From RTL to a placed, routed design that meets timing.
- Timing constraints (SDC) authored with the design
- Clock-tree analysis, setup and hold optimisation
- Power-aware synthesis
Synthesis · Place and route · SDC
- 04
PS-PL integration
The processor and the fabric working as one system.
- Custom AXI peripherals and DMA engines
- Interrupt routing between fabric and processor
- PetaLinux and bare-metal software on the processor
Zynq-7000 · Zynq UltraScale+ · Versal
- 05
FPGA prototyping for ASIC
Prove an ASIC architecture on an FPGA before tape-out.
- Architecture validation and proof of concept
- Performance benchmarking on real hardware
- Pre-silicon verification on the FPGA
Pre-silicon · Tape-out preparation
02 How we work
Verification starts with the RTL, not after it.
Testability is built into the architecture, coverage goals are set before simulation begins, and timing constraints are written alongside the design. Hover a stage to see its part of the flow.
Specification to working board Design · Verify · Integrate
- 01 Spec Architecture
- 02 RTL VHDL · SV
- 03 Constraints SDC
- 04 Simulate UVM
- 05 Coverage Closure
- 06 CDC Clock domains
- 07 Synthesis Netlist
- 08 Place, route Timing
- 09 Bitstream Device image
- 10 Bring-up On the board
-
01
Design
- Architecture
- review and micro-architecture spec before RTL
- RTL
- VHDL and SystemVerilog, testability built in
- Interfaces
- AXI, APB and AHB, custom IP
- Constraints
- SDC written alongside the design
FPGA design work on Defence and SHAR programmes
-
02
Verify
- Testbench
- UVM, constrained-random stimulus
- Coverage
- closure targets set before simulation
- Clock domains
- CDC and RDC analysis
- Assertions
- assertion-based and formal checks
-
03
Integrate
- Timing
- synthesis, place and route, closure
- PS-PL
- Zynq, Zynq UltraScale+, Versal
- Software
- PetaLinux and bare-metal
- Hardware
- validation on boards with real interfaces
Beyond the fabric
-
The board around it
Schematic and multilayer PCB layout, so the RTL, the board and the bring-up are planned together.
Hardware design → -
The software on it
Bare-metal, RTOS and driver code for the processor side of a Zynq or Versal design.
Embedded software → -
In space programmes
Processor and FPGA boards for onboard computing, and FPGA processing for payload electronics, ready to contribute.
Space and satellite →
03 Platforms
Three device families, one verification flow.
GSAS designs across the three FPGA vendors below and their tool chains, and simulates on Questa FPGA Essentials from Siemens EDA.
-
01
AMD (Xilinx)
Device families
- Artix-7
- Kintex-7
- Zynq-7000
- Zynq UltraScale+
- Versal
Tools
Vivado · Vitis · PetaLinux
-
02
Intel (Altera)
Device families
- Cyclone V
- Arria 10
- Stratix 10
- Agilex
Tools
Quartus Prime · Platform Designer
-
03
Lattice
Device families
- ECP5
- CrossLink-NX
- CertusPro-NX
Tools
Radiant · Propel
Tools and boards GSAS supplies for this work
-
Siemens EDA
Questa FPGA Essentials
Mixed-language simulation with UVM support and FPGA vendor libraries.
View product → -
Digilent
Zybo Z7
Zynq-7020 board for PS-PL integration, with HDMI in and out.
View product → -
Digilent
Genesys ZU
Zynq UltraScale+ board with quad Cortex-A53, DDR4 and FMC.
View product → -
Arm
Arm MPS3 FPGA Prototyping Board
Kintex UltraScale board for Cortex-M, -A and -R prototyping images.
View product →
04 Working together
Three ways to start, depending on where the design is.
A new design, existing RTL that needs verifying, or an ASIC that needs proving first. Pick yours.
-
01
Design to your specification
New designs and IP
Send the specification or the block diagram. GSAS takes it from micro-architecture through RTL, verification and timing closure to a design that runs on your target device.
-
02
Verify a design you have
Existing RTL
Bring the RTL you already have. GSAS builds the UVM environment, the coverage model and the clock-domain checks around it, on Questa FPGA Essentials.
-
03
Prototype an ASIC on FPGA
Pre-silicon
Map the ASIC architecture onto an FPGA to validate it, benchmark it on real hardware and verify it before committing to tape-out.
05 Contact
Starting an FPGA design? Start with the specification.
Tell us the device, the interfaces and what the design has to do. GSAS engineers reply with an approach and a proposal: RTL, verification, timing closure and integration, from one team.
Questions
FPGA design with GSAS in India
What FPGA design services does GSAS offer in India?
RTL design in VHDL and SystemVerilog, UVM verification, synthesis and timing closure, processor-to-fabric (PS-PL) integration on Zynq-7000, Zynq UltraScale+ and Versal, and FPGA prototyping for ASIC designs. GSAS works from specification through a verified, timing-closed design.
Which FPGA platforms and tools does GSAS work with?
AMD (Xilinx) Artix-7, Kintex-7, Zynq-7000, Zynq UltraScale+ and Versal with Vivado, Vitis and PetaLinux; Intel (Altera) Cyclone V, Arria 10, Stratix 10 and Agilex with Quartus Prime and Platform Designer; and Lattice ECP5, CrossLink-NX and CertusPro-NX with Radiant and Propel. Simulation and verification run on Questa FPGA Essentials from Siemens EDA.
Can GSAS integrate custom logic with the processor on a Zynq or Versal device?
Yes. GSAS builds custom AXI peripherals and DMA engines in the fabric, routes interrupts to the processing system, and brings up PetaLinux or bare-metal software on the Arm cores, so the processor and the programmable logic are delivered as one working system.
Can GSAS prototype an ASIC on an FPGA?
Yes. GSAS maps ASIC designs onto FPGAs for architecture validation, proof of concept, performance benchmarking and pre-silicon verification, so problems surface before tape-out rather than after it.
Does GSAS also design the board the FPGA sits on?
Yes. The same team covers schematic and multilayer PCB layout, so the RTL, the board and the bring-up are planned together. For space programmes, GSAS is ready to contribute processor and FPGA boards for onboard computing and FPGA processing for payload electronics.
Where is GSAS FPGA work done?
Engineering is led from Bengaluru, India, with GSAS offices in Hyderabad, Chennai, Pune, Mumbai and Delhi NCR among others. GSAS is ISO 9001:2015 certified by TÜV Rheinland.
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