ZedBoard FPGA-in-the-Loop: HDL Verifier vs HDL Coder

A recurring request reaches our application engineers in roughly this form: the team wants to use an FPGA development board for FPGA-in-the-Loop with MATLAB, and has been told the tools for the job are HDL Coder and SoC Blockset.

The board choice is usually sound. The product list is not, and the gap costs real time, because it procures a toolchain that does not include the thing that actually performs FPGA-in-the-Loop.

FPGA-in-the-Loop is HDL Verifier

FIL is a feature of HDL Verifier. HDL Coder does not provide it.

The confusion is understandable. HDL Coder is the product everyone associates with “MATLAB to FPGA”, and it does host the HDL Workflow Advisor, which is one of the two ways to launch a FIL run. But the FIL capability itself, the generated communication logic, the board interface, the synchronisation, lives in HDL Verifier and its board support package.

Here is the split that matters when you are writing a purchase requisition:

Plus the HDL Verifier Support Package for AMD FPGA and SoC Devices, the free add-on that carries the ZedBoard board definition and the AMD tool integration.

If your project genuinely is model-based design, you will end up owning HDL Coder as well, and the pairing is the right one. The point is that ordering HDL Coder and SoC Blockset without HDL Verifier gets you a toolchain that cannot run FIL.

What FIL actually does to your design

HDL Verifier takes your device-under-test HDL and augments it with generated communication logic, assembles that into an FPGA project, and runs synthesis, place and route and bitstream generation. It programs the board, then runs your MATLAB or Simulink simulation with the FPGA strictly synchronised to it.

The synchronisation is the important part. In the default lockstep mode the FPGA clock is gated so the design advances exactly one step per simulation step. That is what makes lockstep FIL cycle-accurate, and it is also what makes it not real-time. HDL Verifier also offers a free-running mode where the hardware clock runs continuously inside the FPGA, which the ZedBoard supports over its Ethernet interfaces. FIL answers “does my logic produce the right results in real silicon, against my real testbench vectors” far more convincingly than simulation alone. It does not tell you how the design performs at speed. That is a different question, and SoC Blockset and on-target profiling are the tools for it.

Is the ZedBoard supported for FPGA-in-the-Loop? JTAG, Ethernet and USB Ethernet

The ZedBoard is listed by name in the MathWorks supported-hardware table for FPGA verification in the current release (R2026a), under the Zynq device family, with the note that the USB port marked PROG is used for programming and that the board supports Processing System Ethernet. It is a predefined board, so you do not need the New FPGA Board Wizard, which exists for boards MathWorks does not support out of the box.

Now the part that matters, because it is actively costing people time.

Search for “ZedBoard FPGA in the loop” and you will find a MathWorks Answers post stating the ZedBoard supports JTAG only. That post is from August 2015. It was correct then. It is not correct now: Ethernet FIL for Zynq boards was added in R2022b. In the current release the ZedBoard is supported over JTAG, Ethernet and USB Ethernet. PCI Express is not supported on this board, which is unsurprising given the XC7Z020 in the CLG484 package has no gigabit transceivers.

JTAG or Ethernet: a real trade-off

Both work. The decision is about setup cost versus throughput.

JTAG is the low-setup path. You need the board, the bundled micro-USB cable into the PROG port, Vivado installed, and factory-default jumpers. No operating system on the Arm cores, no SD card image, no network configuration on the host. For a first FIL run, or for a design where the data volume per simulation step is modest, this is the right choice, and it is the one we recommend teams start with. The cost is transfer speed: JTAG is materially slower than Gigabit Ethernet.

Ethernet is faster but carries a setup tail. On a Zynq device the Ethernet port hangs off the Processing System, not the programmable logic, so host-to-board Ethernet requires software running on the Arm cores. Concretely that means:

• Writing the MathWorks-supplied SD card image, which contains the embedded software and the FPGA programming file that let the board act as an I/O peripheral
• Setting the boot-mode jumpers for SD card boot
• A dedicated Gigabit NIC on the host, or a USB 3.0 Gigabit Ethernet adapter, with a direct cable to the board rather than a path through the corporate LAN
• Static IP configuration on that host adapter

None of it is difficult, but all of it is a place to lose an afternoon the first time, and MathWorks automates the host NIC configuration only on Windows: Linux hosts are supported, but you configure the adapter by hand following the manual setup steps.

Our practical advice: get the design working over JTAG first, so that when you switch to Ethernet you are debugging the transport and nothing else.

How to run FPGA-in-the-Loop: FIL Wizard or HDL Workflow Advisor

If you already have hand-written HDL, use the FIL Wizard. Type filWizard at the MATLAB prompt, or find it in the Simulink toolstrip under Apps, then Code Verification, Validation and Test. The wizard walks through FIL options, source files, device-under-test I/O ports, output types, build options, the build, and finally integrating the generated block back into your model.

If you are generating HDL from a Simulink model, use the HDL Workflow Advisor in HDL Coder. Set Target workflow to FPGA-in-the-Loop in step 1.1; the FIL settings then appear at step 4.1, Set FPGA-in-the-Loop Options. The advisor drives generation, synthesis and simulation in sequence. If you are going MATLAB-to-HDL instead, set Workflow to Generic ASIC/FPGA and select Verify with FPGA-in-the-Loop under HDL Verification.

Same destination, different entry point. The wizard route is often quicker for a team that already has an RTL codebase and wants hardware-backed regression against their existing MATLAB testbenches.

Where SoC Blockset fits: Zynq-7000 hardware-software co-design

A team that names SoC Blockset is usually thinking beyond verification to deployment. That is a separate workflow from FIL.

SoC Blockset models the DDR memory and the shared-memory transactions between the programmable logic and the Arm cores. It lets you configure DMA controllers and arbitrate memory traffic, and it provides performance diagnostics and software profiling so you can find where a design will stall before you commit to hardware. SoC Builder then automates the deployment: building the IP cores and the software, driving Vivado, and programming the board, working alongside HDL Coder and Embedded Coder.

The ZedBoard is supported by SoC Blockset for Zynq-7000, and it is one of the boards covered by the Default System reference design, alongside the ZC706 and the UltraScale+ ZCU102 and ZCU106 kits. Supported add-on cards for the Zynq-7000 entry include the FMCOMMS2, FMCOMMS3 and FMCOMMS4 RF cards and the FMC-HDMI-CAM.

So a complete ZedBoard model-based design programme usually looks like: HDL Coder to generate the logic, HDL Verifier to verify it in real silicon with FIL, SoC Blockset to architect the memory and data movement, Embedded Coder to generate the processor-side software. Four products, four distinct jobs.

Common ZedBoard FIL setup problems: Vivado version, hdlsetuptoolpath, board files

A short list of what our engineers see most:

• Vivado version mismatch. MathWorks pins supported third-party tool versions per MATLAB release. Installing the newest Vivado and assuming it works produces build failures that look like FIL problems and are not. Check the supported-tool table for your specific release.
• hdlsetuptoolpath not run. MATLAB has to be told where Vivado lives. Without it, synthesis simply does not start.
• Board files not installed. Digilent’s board files make the ZedBoard a selectable target with the Processing System pre-configured for the right DDR3, clocks and MIO. Without them you are configuring the Processing System by hand against the hardware user’s guide.
• Ethernet FIL over a corporate LAN. MathWorks does support running FIL over a network rather than a direct cable, but the guided setup assumes a dedicated adapter with a static address, and a shared office network adds DHCP, VLAN and firewall variables to a bring-up you want boring. Start with a direct cable.
• Following a Vitis Classic tutorial on a 2025 or later toolchain. AMD removed the Classic Vitis IDE in the 2025.1 release. The hardware steps in older ZedBoard tutorials still hold, but every software project creation step has to be redone in Vitis Unified.

Vivado licensing and AMD tool downloads in India

Two questions come up in every Indian procurement conversation, so to answer them directly.

Do you need a paid Vivado licence? No. AMD moved Vivado to subscription tiers at the 2026.1 release, replacing the older edition names (WebPACK, later Vivado ML Standard Edition). Zynq-7000 devices are available in every tier including the entry-level Basic tier, which AMD provides at no cost with an annual licence renewal. Budget for the board and the MathWorks licences, not for the AMD toolchain.

Can Indian users download AMD tools? Yes. Digilent’s ZedBoard page carries a general warning that AMD tools are not downloadable in some countries, which reasonably worries buyers here. AMD’s export compliance policy restricts downloads to countries outside US Country Groups D and E; India is in Country Group A in the current tables and is not in D or E. Indian engineers register and download normally. Individual accounts can still be held for non-country reasons, an incomplete company address, a PO Box, or a VPN masking the originating IP, so do not read a per-account hold as a country block.

Buying a ZedBoard for FPGA-in-the-Loop in India

If you are scoping a ZedBoard FIL project in India, GSAS Micro Systems supplies the ZedBoard as an authorized Digilent engineering partner, and our application engineers in Bengaluru, Hyderabad, Chennai, Pune, Mumbai and Delhi NCR work through the toolchain setup with customer teams. If you are still choosing hardware, the Zybo Z7 and Eclypse Z7 are the alternatives worth weighing, and our Vivado getting-started guide covers the ground before the MathWorks layer goes on top.

Sources: MathWorks HDL Verifier, HDL Coder, SoC Blockset and Embedded Coder product and support-package documentation; MathWorks supported-hardware tables for FPGA verification and SoC Blockset; MathWorks HDL Verifier R2022b release notes; AMD Vivado release notes and installation guide (UG973); AMD export compliance notice; 15 CFR Part 740 Supplement No. 1 country groups; Avnet ZedBoard Hardware User’s Guide.