Embedded Perspectives
Technical Guides
50 articles tagged with Technical Guides.
ZedBoard FPGA-in-the-Loop: HDL Verifier vs HDL Coder
Teams asking for FPGA-in-the-Loop on a ZedBoard usually name HDL Coder and SoC Blockset. FIL is actually HDL Verifier. Here is the correct product split, the JTAG versus Ethernet decision, and the 2015-era advice that is still sending Indian teams down the wrong path.
FADOS Test Reports and GSAS Agent: Turning Board Test Results into an Auditable Record
A pass or fail on the FADOS screen is not a record. This guide covers what the FADOS test report contains, what GSAS Agent does with it, and how offline, Google Drive and LAN modes put a QR-linked report on the job card for repair shops and EMS lines in India.
Test Case Design with the Classification Tree Method: Deriving Unit Tests You Can Defend in an Audit
Ad-hoc test cases can be perfectly good tests and still fail an audit, because nothing on file records why that particular set was sufficient. The Classification Tree Method derives test cases from the input space instead: identify the test-relevant aspects as classifications, partition each into equivalence classes, then combine leaf classes in a combination table. Razorcat implements CTM in the Classification Tree Editor, available integrated into TESSY or standalone. GSAS Micro Systems is the authorized Razorcat engineering partner for India, the UAE and Sri Lanka.
Fault Injection and Robustness Testing for Embedded Software: What ISO 26262, IEC 61508 and DO-178C Actually Ask For
Every safety-related unit contains code that correct inputs never execute: range checks, error returns, timeouts, recovery paths. The functional safety standards require that code to be verified, and they are explicit about how. ISO 26262-6 lists fault injection test as a method for both software unit verification and software integration verification; IEC 61508-3 recommends defensive programming from SIL 2 upward and then concedes that defensive code is exactly what stops teams reaching 100 percent structural coverage. This guide separates robustness testing from fault injection, maps each to the obligation that asks for it, and shows how Razorcat implements automated fault injection in TESSY without leaving instrumentation in production code.
How to Evaluate a Unit Testing Tool for Embedded Software: A Buyer's Framework for Indian Teams
Unit test tool evaluations rarely fail on features. They fail because the tool cannot drive the compiler and debugger the project is already committed to, or because the evidence it produces sits outside the scope of the certificate the assessor asks for. This is a buyer-side framework: six questions, what a credible answer looks like in vendor documentation, and a four-week pilot that measures the answers instead of accepting them.
Is 100% Code Coverage Enough? Statement, Branch, MC/DC and MCC, and What Each One Proves
No. A coverage percentage records which code your tests executed, not whether your tests would notice if that code were wrong. This guide defines statement, branch, decision, condition/decision, MC/DC and multiple condition coverage precisely, sets out what 100% of each does and does not prove, shows what ISO 26262, IEC 61508 and DO-178 ask for alongside coverage, and explains the three things to add: requirements traceability, fault-based testing and robustness cases.
Automated Mutation Testing for Embedded C: The Question MC/DC Coverage Cannot Answer
Structural coverage tells you a line was executed. It does not tell you that a defect in that line would have been caught. Mutation testing closes that gap by seeding small faults into the code, re-running the suite, and counting how many the suite kills. This guide covers mutation operators, the mutation score, the equivalent-mutant problem and cost control, and where seeded faults already sit inside IEC 61508-3. GSAS Micro Systems is the authorized Razorcat engineering partner for India, the UAE and Sri Lanka.
Test Case Quality in Embedded Unit Testing: Why Test Counts and Coverage Are Weak Proxies
Counting test cases and reporting a coverage percentage tells you what your tests touched, not what they would have caught. NASA's tutorial on modified condition/decision coverage puts it directly: coverage is a measure, not a method or a test. A good unit test case traces to a requirement, carries an expected result predicted from the specification, draws its inputs from equivalence classes and boundary values, and stays independent of how the code happens to be written. This guide sets out those four properties, shows how coverage-adequate suites still miss defects, and maps them to ISO 26262 Part 6, DO-178C and IEC 61508 expectations for requirements-based testing.
From Evaluation Licence to Production Licence: How Embedded Unit Test Tool Licensing Actually Works in India
A unit test tool licence is not paperwork at the end of an evaluation, it is a project constraint. Razorcat's own License Management Guide documents the whole arc for TESSY: an evaluation key issued against one host Id and delivered the next working day, a Floating License Server reached over a single TCP port, offline checkouts capped at 3 days by default and 30 as the built-in maximum that cannot be given back, access control lists and usage logging for seat planning, and a separate Continuous Integration licence that the TESSY IDE cannot use. This guide walks that arc and then the part no vendor manual covers: getting the purchase order through GeM, SAP Ariba, Coupa or TReDS.
Unit Testing Fundamentals for Embedded C and C++: Units, Interfaces, Test Drivers, Stubs and What the Safety Standards Demand
In C a unit is a single function. In C++ it is a method, and a method cannot be called without an object. Everything else in unit testing follows from that: the interface is what the unit reads and what it writes, a test driver supplies the startup code and the call, and stubs replace the units around it so the result depends on the unit alone. Razorcat's published TESSY documentation, IEC 61508-3 and the airworthiness authorities all describe the same discipline, and the functional safety standards write it as normative text rather than advice.
I3C FAQ for Firmware Teams: What the Bus Is, What Changes, and What You Need on the Bench
MIPI Alliance describes I3C as the successor to I2C, with legacy compatibility so that I3C and I2C devices can coexist on the same bus, a two-wire interface that supports in-band interrupts to reduce pin count, plus multi-controller support and dynamic addressing. This FAQ answers the questions firmware teams actually ask before adopting it.
Running the Binho Supernova as an I3C Target: Emulating a Device Against Your Own Controller
Binho specifies the Supernova's I3C role as Controller or Target, which means the same adapter can stand in as the device under test rather than only driving one. That second direction is how a team validates its own I3C controller, its ENTDAA implementation and its interrupt handling, before the target silicon exists.
Arm User-Based Licensing in CI/CD: armlm, Proxy Activation and What Breaks
A licensing failure in an Arm pipeline blocks the release branch and puts a firmware engineer on armlm output instead of driver code, up to seven days after the change that caused it. The reason: a UBL licence is a cached certificate valid for 7 days, not a checkout. Here is what that changes about pipeline design, and what to fix first.
Undefined Behaviour in Embedded C and C++
Undefined behaviour is not a bug your compiler owes you a warning about. ISO/IEC 9899 defines it as behaviour for which the standard 'imposes no requirements', and it signals it in three different ways with, in the standard's own words, 'no difference in emphasis' between them. Which is why code carrying undefined behaviour can pass every test on your bench and still change the day you upgrade the toolchain.
SEGGER J-Link and J-Trace Now Support Andes Trace: Why This Matters for RISC-V
SEGGER's J-Link and J-Trace probes now support Andes Trace, the hybrid N-Trace plus E-Trace instruction-trace solution built into Andes RISC-V cores. Here is what Andes Trace is, why probe-level support closes one of RISC-V's last serious tooling gaps, and what it means for Indian embedded teams.
AI Data Center Testing: Power Shelves, Busbars, Burn-In and Optics
AI racks fail on the bench long before they fail in the field. How AI data center infrastructure is actually tested: server power shelves and CRPS supplies, 48V busbars, battery backup units, DC-DC stages, burn-in, thermal validation, high-speed switches, and optical transceivers, mapped to the GW Instek instruments GSAS supplies across India.
Siemens EDA EBS Expert Series: 6 Free PCB Design Webinars (Jul-Aug 2026)
Siemens EDA is running six free EBS Expert Series webinars from 22 July to 27 August 2026, covering HyperLynx PI DC Drop analysis, Xpedition DRC, Xpedition EDM and PLM integration, EDX, and Starpoints/Tiebars net shorting. GSAS, an authorized Siemens EDA engineering partner in India, is highlighting all six for Indian PCB design teams.
J-Link Remote Server: Shared Debug Probes, Remote Debugging, and CI/CD Test Farms
Any USB J-Link can be shared over the network with SEGGER's free J-Link Remote Server, and the J-Link PRO puts itself on Ethernet directly. Here is how Indian firmware teams build shared labs, debug hardware across sites, and wire J-Link into CI/CD.
Unlimited Flash Breakpoints Explained: How J-Link Does It and Which Models Include the License
Cortex-M silicon gives you 4 to 6 hardware breakpoints. SEGGER's Unlimited Flash Breakpoints removes the ceiling by reprogramming flash on the fly. Here is how the technology works, what it costs in wear and speed, and exactly which J-Link models include the license.
Hardware-Free CI/CD Regression Testing for Embedded Teams in India
Embedded regression suites are often bottlenecked by how many test boards a team owns. SEGGER's Ozone-Sim runs Arm and RISC-V firmware headless in CI, with built-in semihosting for test parameters and logged results, so regression testing no longer waits on hardware availability.
Ozone-Sim: SEGGER's Hardware-Free Embedded Simulator for Arm and RISC-V
SEGGER's new Ozone-Sim instruction set simulator runs Arm and RISC-V firmware on a PC at hundreds of millions of instructions per second (up to 700 million on an AMD Ryzen 9, per SEGGER), no J-Link and no target board required. Here is how it works with Ozone, how it plugs into CI/CD, and how to evaluate it in India with GSAS.
Testing High-Power UPS, Solar Inverters and Power Electronics: Inside the GW Instek AEL-5000 AC/DC Electronic Load
India's UPS, solar-inverter and power-electronics makers need load testing that behaves like the real world: non-linear, high-power and scalable. Here is how the GW Instek AEL-5000 AC/DC electronic load covers it, from 1.875 kW on the bench to 540 kW in a three-phase array.
Automated EV Charger Test Bench in India: GW Instek AC Source, DC Load and Battery Emulator
A walkthrough of an automated test bench that validates a CAN-controlled EV scooter charger across the full Indian grid envelope. GW Instek's APS-7200 AC source, PEL-3111AH DC load and GPP-7250 battery emulator combine with a Total Phase Komodo CAN Duo BMS emulator for unattended, repeatable charger validation, designed, integrated and scripted in India by GSAS.
Best Logic Analyzer in India (2026): A Vendor-Neutral Buying Guide for Embedded Teams
Channels, sample rate, protocol decode, and streaming vs buffer, a vendor-neutral buying framework for choosing a USB logic analyzer or protocol analyzer in India, funnelling to the SKUs that actually fit your bus.
How to Buy an Oscilloscope in India (2026): USB vs Benchtop, Bit Depth, Bandwidth: A Buying Guide
A vendor-neutral buying guide for Indian engineering teams choosing an oscilloscope in 2026. How to size bandwidth, sample rate, channels and bit depth; when a USB/PC oscilloscope beats a benchtop; and how oscilloscope price in India actually breaks down once you add GST, probes and warranty. Written for embedded, power and education teams in Bengaluru, Pune, Chennai, Hyderabad, Mumbai and Delhi NCR.
GW Instek 6S Catalog: High-Power Test Instruments for India: A Build Guide
GW Instek's 6S line, DAQ-9600 data acquisition, the PHU autoranging DC source, the ASR-6000 AC/DC power source, and the AEL-5000 / PEL-5000G / PEL-5000C electronic loads, is a complete high-power test ecosystem. Here is what each instrument does, how to combine them into an EV-charger, battery or solar-inverter test bench, and how to buy and integrate the line in India through GSAS.
New from GW Instek (2026): SPS-A Series Switching DC Power Supplies & GDS-2000HD/HG 12-bit Oscilloscopes: Now in India
GW Instek has launched two new instrument families: the SPS-A Series, a new-generation, 360 W single-channel switching DC power supply line with an encoder digital knob and a 2.4-inch colour LCD, and the GDS-2000HD/HG Series, a compact 12-bit oscilloscope with an Android-based smart UX. Here is what is verified, model by model, and how Indian teams can evaluate, quote and demo both through GSAS Micro Systems.
Shift-Left for Safety-Critical Code: Perforce QAC Static Analysis + Razorcat TESSY Dynamic Testing for MISRA, IEC 62304 and FDA Compliance in India
Run Perforce QAC static analysis first to enforce MISRA and clean the code, then Razorcat TESSY for dynamic unit testing and MC/DC coverage. Together they form a complete shift-left toolchain for IEC 62304 medical-device and FDA-regulated software, both from one authorized engineering partner in India, GSAS Micro Systems.
AI Data Centers in India: Test, Measurement & Memory Boom
AI is a hardware supercycle. Every AI rack has to be designed, brought up, powered, fed with memory, and kept alive, and each of those is a test, measurement and memory problem. Here is the full engineering toolchain behind the AI data center, mapped to what Indian teams can buy today through GSAS.
AI and Intelligent Automation in PCB Design: How Siemens Xpedition Removes the Work That Slows Indian Teams Down
Siemens' own engineers describe a 'productivity paradox' in PCB design: the tools have never been more capable, yet throughput has not kept pace. This is how AI, intelligent automation, design reuse and connected data continuity in Xpedition Standard close that gap, and what it means for PCB design teams in Bengaluru, Pune, Chennai, Hyderabad, Mumbai and Delhi NCR.
JTAG-HS3 vs HS2 FPGA Programming Cable: Boundary Scan, Production & Validation in India
A use-case guide to the Digilent JTAG-HS2 vs JTAG-HS3 FPGA programming cables for the engineers who actually rely on them, memory-validation bench teams, defence and aerospace FPGA production lines, and high-volume EMS boundary-scan test. Specs, IEEE 1149.1 structural test, production flash programming, and which cable to buy in India.
From Discovery to Production: The Modern PCB Design Journey in Siemens Xpedition: for Indian Teams
Siemens' Xpedition walkthrough 'From discovery to production' traces a single connected PCB journey, AI-assisted circuit discovery, cloud-connected tuning and simulation, AI-assisted command prediction, real-time supply-chain analysis, online design reviews, and manufacturability analysis with price estimation. Here is what that flow means for PCB design teams in Bengaluru, Pune, Chennai, Hyderabad, Mumbai and Delhi NCR, and how GSAS can share it when you ask.
Logic Analyzer vs Oscilloscope vs MSO: When You Actually Need Analog Channels (Saleae Logic MSO)
A decision tree for Indian embedded teams: logic analyzer, oscilloscope, or mixed-signal oscilloscope? A channel-count heuristic, the three questions that actually decide it, and when 4 real analog channels in a Saleae Logic MSO beat buying a separate benchtop scope plus a separate logic analyzer.
MCC USB DAQ Selection Guide for Indian Labs: USB-1808X vs USB-1608G vs MCC 118
Choosing an MCC USB data acquisition device for an Indian lab comes down to three questions: do you need simultaneous sampling, how many channels, and Raspberry Pi or PC? This guide compares the MCC USB-1808X, USB-1608G Series, and MCC 118 DAQ HAT.
Debugging Automotive CAN, CAN-FD and LIN with Saleae Logic 2: A Bench Workflow for Indian ECU Teams
The protocols on every automotive ECU bench in India, CAN, CAN-FD and LIN, debugged the right way with Saleae Logic 2. Where to probe, how to decode, and the single-ended caveat clone sellers never explain.
Saleae vs Cheap USB Logic Analyzers: Is the Genuine Saleae Worth It for Indian Embedded Teams?
A ₹500 FX2 clone and a genuine Saleae both decode I²C, until the bug doesn't repeat, the rail glitches, or the input sees 12 V. An honest, attribution-safe contrast for Indian embedded teams about to raise a PO.
SWD & JTAG Debug-Port Isolation Explained: Protecting Your Probe, PC & Engineers (SEGGER J-Link, Flasher & J-Trace Isolators)
Plugging a USB-grounded debug probe into a motor drive, inverter, or high-voltage battery board can destroy the probe, fry your laptop's USB controller, or expose an engineer to a hazardous potential. Here is how SWD/JTAG debug-port isolation actually works, why SEGGER ships separate target-side and host-side isolators, and how Indian power-electronics, EV, and industrial teams should specify them, with verified specs only.
USRP SDR Selection Guide for India: B200mini, B205mini-i, B210, X310 and E320
Picking the right USRP software-defined radio for an Indian RF lab, telecom prototype, or embedded sensing node depends on channels, bandwidth, host link, and whether you need standalone operation. This guide compares the NI Ettus USRP B200mini, B205mini-i, B210, X310 and E320.
Saleae High-Level Analyzers (HLAs): Building Custom Protocol Decoders in Python
When Saleae's 23 built-in plus 50+ community protocol analyzers don't cover your application-layer needs, you write your own decoder in Python. A walkthrough of the HLA framework with a working example for Indian embedded teams.
Decoding I²C, SPI, and UART with Saleae Logic 2: A Bring-up Workflow for Indian Embedded Teams
The three protocols every embedded engineer in India will debug this year. Practical Saleae Logic 2 capture, trigger, and decode patterns for I²C, SPI, and UART bring-up, without the marketing fluff.
Saleae Python API for CI/CD: Capturing Protocol Traces in GitHub Actions
The Logic 2 Automation API drives Saleae devices from Python. Here's how Indian embedded teams wire it into a GitHub Actions or GitLab CI workflow for nightly hardware-in-the-loop regression on a bench Raspberry Pi.
Saleae Logic MSO in India: Why the New Mixed-Signal Line Matters
Saleae's new Logic MSO line replaces 'benchtop scope + separate logic analyzer' with a single USB pod. Three variants, MSO 2×100, 4×100, 4×200, at 100–200 MHz analog bandwidth with 8 (expandable to 20) digital channels. India-focused selection guide and use cases.
HyperLynx 2604: Every New Feature for India's Signal & Power Integrity Teams
HyperLynx 2604 lands with parallelised DDRx batch simulation, PCIe Gen 7 PAM4 compliance, a Time-Domain PDN wizard, GDSII reassignment and an in-app Product Support Copilot, here is what each release video actually shows, and what it means for SI/PI teams in India.
Saleae Logic Pro 16 vs Logic Pro 8 vs Logic 8: Picking the Right Analyzer for Indian Embedded Teams
Channel count, sample rate, threshold flexibility, and the cost-of-being-wrong, a buying decision framework for Indian embedded teams choosing between the three current Saleae Logic SKUs.
SEGGER Monitor Mode Debugging: When Halting the CPU Breaks the Motor
Setting a breakpoint on a motor-control or DC-DC firmware target halts the PWM and lets the motor freewheel, or worse. SEGGER's Monitor Mode debugging keeps the time-critical interrupts running while the rest of the code halts. Here's how it works on Cortex-M, when to reach for it, and how Indian power-electronics teams use it.
Siemens EDA 2026-04 Release Recap: What Changed in Xpedition, HyperLynx, and Valor for India Teams
Siemens shipped Xpedition 2604, HyperLynx 2604, and Valor NPI 2604 together, a coordinated release that touches PCB layout, signal/power integrity, and manufacturing sign-off. Here is the single index to all three deep-dives, with a guide to which teams in India should read what.
Accelerating PCB Design with AI, Reuse, and Connected Workflows: for India's Engineering Teams
How Siemens Xpedition Standard combines AI-powered design entry (CELUS), placement and routing automation, hierarchical reuse blocks, and Blueprint release powered by Valor, and what that combination changes for PCB teams in Bengaluru, Pune, Chennai, Hyderabad, Mumbai and Delhi NCR working under real Indian deadlines.
Valor NPI 2604: Every New Feature for India's PCB Manufacturing and DFM Teams
Valor NPI 2604 brings IPC-4761 via-type awareness into DFM, migrates sliver and acute-angle checks into the Analysis Definition Manager, validates SMD/BGA pad-perimeter copper coverage, and lands new through-hole lead-length constraints. Here is what changes for Indian PCB fabricators, EMS NPI desks and DFM engineers.
Xpedition 2604: Every New Feature That Matters for India's PCB Design Teams
Siemens Xpedition 2604 ships AI-assisted help, multi-board signal matching, web check-in/out, integrated BluePrint documentation, creepage checks, IPC-4761 vias and DFM during team layout, here is what each new capability does, with every demo video re-embedded.
SEGGER J-Trace PRO: Streaming Trace That Catches Bugs You Can't Reproduce
SEGGER J-Trace PRO delivers unlimited streaming trace, live code coverage and profiling for Arm Cortex-M, Cortex-A/R and RISC-V, the tool that finally catches the bug that won't reproduce on the bench.