RTL design and IP
Digital design from specification to synthesis-ready RTL that meets timing.
- Custom IP cores and configurable modules
- AXI, APB and AHB bus interfaces
- Timing constraints, synthesis and timing closure
Industries · Semiconductor Design
From RTL to first silicon, designed, verified and brought up in India.
RTL design and UVM verification, FPGA prototyping before tape-out, evaluation boards, first-silicon bring-up on Arm and RISC-V, and power and interface characterisation on the bench. Engineering led from Bengaluru.
01 The challenge
From RTL to Silicon Validation.
RTL design, UVM verification, FPGA prototyping, first-silicon bring-up and bench characterisation for semiconductor teams in India.
Semiconductor programmes run from RTL design through verification, first silicon and production test, and each hand-off is a chance for a problem to escape into the next, more expensive stage. Teams building Safety Elements out of Context (SEooC) for automotive, or high-performance application processors, also need the software and the boards ready when silicon arrives, so the gap between hardware design and software enablement does not hold up the chip’s first customers.
GSAS works across that lifecycle. Before tape-out, it writes RTL, builds UVM testbenches and prototypes ASIC designs on FPGAs. When silicon arrives, it designs the evaluation board and brings the chip up: J-Link PRO provides the debug connection for first-silicon bring-up and software enablement on Arm Cortex-M, Cortex-A, Cortex-R and RISC-V targets.
On the bench, the Joulescope JS320 profiles current across power states to validate power-management IP, and PicoScope provides the mixed-signal analysis for chip-to-chip interfaces during board bring-up. GSAS also supplies Arm and Siemens EDA tools, so the design, verification and debug tool chain and the engineering around it come from one team in India.
02 What we engineer
Six semiconductor services, mapped onto the chip lifecycle.
Each card lights the stage of the silicon lifecycle that service touches, from the first line of RTL to a chip characterised on the bench.
- 1. RTL and IP: VHDL, SystemVerilog
- 2. Verification: UVM, coverage, lint
- 3. FPGA prototype: Pre-silicon validation
- 4. Evaluation board: Schematic, layout, SI/PI
- 5. First silicon: Bring-up, BSP, drivers
- 6. Bench and test: Power, timing, production
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-
UVM verification
Testbenches written alongside the design, reusable when it moves from FPGA to ASIC.
- Constrained-random UVM testbenches with scoreboards
- Functional coverage models and assertion-based checks
- RTL lint gates and CDC methodology for multi-clock designs
-
FPGA prototyping for ASIC
An ASIC architecture proved on an FPGA, so problems surface before tape-out rather than after it.
- Architecture validation and proof of concept
- Performance benchmarking on real hardware
- Pre-silicon verification on the FPGA
-
Evaluation and reference boards
The board a new chip is evaluated, demonstrated and brought up on.
- Power tree, rail budgeting and component selection
- Multilayer layout with controlled impedance and BGA fan-out
- Signal and power integrity on high-speed interfaces
-
First-silicon bring-up
From silicon evaluation to board support that customers of the chip can build on.
- Clock tree, memory controller and peripheral initialisation
- Drivers, BSPs and embedded Linux device trees
- Arm Cortex-M, Cortex-A, Cortex-R and RISC-V targets
-
Bench characterisation and test
Power states, interfaces and timing measured on real silicon, then carried into production test.
- Power-state current profiling for power-management IP
- Protocol capture and signal integrity on chip-to-chip links
- Automated test stations under SCPI and VISA control
03 How we work
Down the silicon lifecycle, with a check at every step.
The same discipline from RTL to a chip on the bench: each stage leaves something the next team, the tape-out review or the chip’s first customers can check.
-
01
Design
- RTL
- IP cores, bus interfaces, DSP pipelines
- Constraints
- SDC timing constraints written with the design
- Lint
- RTL checked before the first simulation
Synthesis-ready RTL with timing closed
-
02
Verify and prototype
- Testbench
- Constrained-random UVM with scoreboards
- Coverage
- Functional coverage and assertions
- Prototype
- The design running on an FPGA board
Problems found before tape-out, not after it
-
03
Bring up
- Board
- Evaluation board designed for the chip
- Software
- Clocks, memory, drivers and BSP on first silicon
- Bench
- Power states, interfaces and timing measured
A chip that boots, talks and is characterised
- Half-acre build and test site, Bengaluru Rural, opened 2026
- Doddaballapur
- Specialists, engineering led from Bengaluru
- 40+
- In 9 Indian cities
- 11 offices
- Certified by TÜV Rheinland
- ISO 9001:2015
04 Capabilities
The GSAS capability pages behind Semiconductor Design.
Each service above is a full practice at GSAS. These are the pages that describe it in depth.
- Embedded Software Engineering First-silicon bring-up and software enablement, BSP development, and debug and trace integration across Cortex-M, Cortex-A, Cortex-R and RISC-V targets.
- Safety & Compliance Engineering Verification evidence and tool qualification documentation for safety-related software on the silicon's reference BSPs.
- Test & Measurement Integration Precision power profiling for power-management IP validation, and high-resolution mixed-signal analysis of chip-to-chip interfaces during board bring-up.
- Training & Enablement Xpedition PCB Layout workshops, Embedded Architecture deep-dives and custom corporate programmes for design centres.
05 Tools
The tools Semiconductor Design teams use, and GSAS engineers use too.
GSAS is a value added distributor/reseller for these products. We have a dedicated FAE team ready to help you with custom built solutions matching your needs.
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SEGGER J-Link PRO Professional JTAG/SWD debug probe with USB and Ethernet connectivity, supporting Arm Cortex-M/A/R and RISC-V architectures. India pricing and local support from GSAS. -
Joulescope Joulescope JS320 Third-generation precision DC energy analyzer with 0.1 nA resolution and a 24-bit measurement path for low-power embedded systems. Available in India from GSAS with hands-on application engineering and local support. -
Pico Technology PicoScope 6000E High-bandwidth USB oscilloscope spanning 300 MHz to 3 GHz bandwidth, FlexRes 8-to-12-bit resolution, and up to 4 GS deep memory. Authorized India partner, GSAS Micro Systems. -
Siemens EDA Calibre Industry-standard IC physical verification and signoff platform, DRC, LVS, parasitic extraction, and pattern matching for advanced-node tapeout. Available in India from GSAS. -
Siemens EDA Tessent Design-for-test (DFT) insertion, ATPG, BIST, diagnosis, and silicon lifecycle management for automotive and high-reliability ICs. Available in India from GSAS. -
Siemens EDA Solido Statistical variation-aware simulation and library characterization for advanced-node analog/mixed-signal IC design. Available in India from GSAS. -
Siemens EDA Questa FPGA Essentials (QuestaSim FPGA Edition) Questa FPGA Essentials (QuestaSim FPGA edition), the Siemens EDA FPGA simulation and verification bundle built on the Questa simulator, with UVM and mixed-language support and an optional RTL lint add-on. Available in India from GSAS, Siemens EDA authorized engineering partner. -
Siemens EDA Innovator3D IC Layout TSMC InFO-certified IC packaging layout tool for 2.5D/3D integration and advanced fan-out wafer-level packaging. Buy in India from GSAS with local support.
06 Standards
Standards listed for Semiconductor Design, and the tools placed against each.
A chip shows a published qualification scope where one exists, and the bare standard name where none does.
AUTOMOTIVE ISO 26262 SEooC No tool mapped
INDUSTRIAL IEC 61508
ISO 26262 SEooC is listed in this page's standards set, but no tool in the table below carries a published qualification against it, and GSAS does not claim one. Whether this applies to a given programme depends on its scope, jurisdiction and certification basis.
| Tool | Applicable Standards |
|---|---|
| Klocwork (Perforce) | IEC 61508 up to SIL 4 |
| Perforce QAC | IEC 61508 up to SIL 4 |
| Arm Compiler for Embedded FuSa | IEC 61508 SIL 3 (qualified releases) |
| embOS-Safe (SEGGER) | IEC 61508 SIL 3 |
| TESSY (Razorcat) | IEC 61508 (T2 support tool) |
07 Working together
Three ways to start, depending on where your chip is.
RTL in progress, silicon arriving in the lab, or an architecture still to prove.
-
01
Semiconductor design centres
RTL and verification capacity
RTL design in VHDL and SystemVerilog, UVM testbenches with coverage models and scoreboards, lint gates and CDC methodology, delivered by a team that can also put the design on an FPGA.
- RTL and IP
- UVM verification
- Lint and CDC
-
02
Silicon and IP enablement teams
First silicon to customer kits
Evaluation boards for a new chip, first-silicon bring-up and BSPs on Arm and RISC-V, and power and interface characterisation that the chip’s customers can rely on.
- Evaluation boards
- First-silicon bring-up
- Bench characterisation
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03
Fabless start-ups
Architecture to tape-out
An ASIC architecture proved on an FPGA, with testbenches that carry forward into the ASIC flow and benchmarks taken on real hardware before the tape-out decision.
- FPGA prototyping
- Reusable testbenches
- Pre-silicon benchmarks
08 Contact
Designing a chip or bringing one up?
Tell us the design, the target and where the programme is. GSAS replies from Bengaluru with scope and a proposal: RTL, verification, FPGA prototyping, boards, bring-up and characterisation.
Questions
Semiconductor Design engineering with GSAS in India
What semiconductor engineering services does GSAS provide in India?
GSAS provides RTL design and IP, UVM verification with coverage and lint, FPGA prototyping for ASIC designs, evaluation board design, first-silicon bring-up and BSPs, and power and interface characterisation on the bench. Engineering is led from Bengaluru.
Can GSAS prototype our ASIC on an FPGA before tape-out?
Yes. GSAS maps ASIC designs onto FPGAs for architecture validation, proof of concept, performance benchmarking and pre-silicon verification, so problems surface before tape-out rather than after it.
Does GSAS write UVM testbenches for RTL designs?
Yes. GSAS designs UVM testbench architecture, implements constrained-random stimulus, coverage models and scoreboards, and adds RTL lint gates to CI. Testbenches built for an FPGA carry forward if the design moves to ASIC.
Can GSAS bring up first silicon and write the BSP?
Yes. GSAS initialises the clock tree, memory controller and peripherals, integrates drivers and builds the board support package on Arm Cortex-M, Cortex-A, Cortex-R and RISC-V targets, including embedded Linux device trees for Cortex-A parts.
Can GSAS design the evaluation board for a new chip?
Yes. The hardware team covers the power tree, multilayer layout with controlled impedance and BGA fan-out, and signal and power integrity analysis, so the board, the RTL and the bring-up are planned together.
Does GSAS also supply the semiconductor design and debug tools?
Yes. GSAS is a value added distributor/reseller for the simulators, EDA tools, debug probes, energy analysers and oscilloscopes on this page, and its engineers use the same tools on customer projects.
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