Calibre Vision AI: Bringing Order to DRC Debug at…

Physical verification at advanced nodes has a coordination problem, not just a computation problem. A full-chip DRC run on a large SoC can return hundreds of millions of violations, spread across blocks owned by different engineers in different places. The run itself is the easy part. Deciding who owns which violations, tracking what has been waived, fixed or ignored, and handing partly-debugged context between a chip integrator and a partition owner is where schedules go to die.

Siemens EDA’s answer is Calibre Vision AI, presented in an August 2026 Calibre blog post as a way to turn that flood into a structured, collaborative process. This article summarises what the tool does and why it matters for Indian SoC teams; the full technical walkthrough is in the Siemens post linked under References.

Calibre Vision AI interface with DRC results organised for triage

Status that survives the debug cycle

The core workflow change is Signal status tracking. Every violation cluster (a Signal, in the tool’s vocabulary) carries a persistent status through the debug lifecycle: Ignored, Assigned, In Progress or Resolved. That sounds mundane, and that is the point. Once status lives in the tool rather than in spreadsheets and hallway conversations, convergence progress is visible in real time, and the question “are we actually closing DRC or just re-running it” has an answer.

Signal status values tracked through the DRC debug lifecycle

Filters that match how chips are actually debugged

Two filter families do the slicing:

Global check filters isolate or exclude specific DRC checks by exact name or wildcard across the whole chip, so a metal-spacing campaign is not buried under antenna violations.
Global cell filters zoom the working set to a block or hierarchical region, which is how partition owners actually work: my block, my violations, nothing else.

Handoff without losing the plot

The third piece is workspace save and export. A debug session, including filter settings, selected Signals and layout views, can be saved and handed to the next engineer intact, and results can be exported as an ASCII database for sharing through Calibre RVE. The chip integrator to partition owner handoff, which traditionally loses context at every hop, keeps it instead.

Why this matters for Indian SoC teams

India hosts a large share of the world’s physical verification work, and the coordination pattern Calibre Vision AI addresses, distributed blocks, distributed owners, one convergence deadline, is the daily reality of SoC teams in Bengaluru and Hyderabad working with counterparts across time zones. A handoff that preserves debug context matters more, not less, when the handoff crosses ten and a half hours.

GSAS supports the Siemens EDA portfolio in India, Calibre included, with local application engineering across Bengaluru, Hyderabad, Chennai, Pune, Mumbai and Delhi NCR. If your team wants to evaluate Calibre Vision AI against a live convergence problem, talk to us.