Embedded Perspectives
Semiconductor Design
19 articles tagged with Semiconductor Design.
I3C FAQ for Firmware Teams: What the Bus Is, What Changes, and What You Need on the Bench
MIPI Alliance describes I3C as the successor to I2C, with legacy compatibility so that I3C and I2C devices can coexist on the same bus, a two-wire interface that supports in-band interrupts to reduce pin count, plus multi-controller support and dynamic addressing. This FAQ answers the questions firmware teams actually ask before adopting it.
Running the Binho Supernova as an I3C Target: Emulating a Device Against Your Own Controller
Binho specifies the Supernova's I3C role as Controller or Target, which means the same adapter can stand in as the device under test rather than only driving one. That second direction is how a team validates its own I3C controller, its ENTDAA implementation and its interrupt handling, before the target silicon exists.
PicoScope Signal Integrity in India: USB 3.x, PCIe, DDR, and Ethernet-APL
How Indian SoC and board teams use PicoScope 6000E, PicoScope 9400A SXRTO, and PicoVNA 108 for USB 3, PCIe, DDR, and Ethernet-APL signal integrity work.
How to Choose an Arm Cortex Processor: A Selection Guide for Indian Embedded Teams
Choosing an Arm Cortex core is a decision about real-time determinism, memory architecture and toolchain, not about clock speed. This selection guide walks Indian embedded teams from workload to short list, including MCU vendors, toolchains and debug probes.
MIPI I3C Adoption in Indian Semiconductor Design Centers
MIPI Alliance lists I3C v1.0 as a 2016 release, and the design centres in Bengaluru and Hyderabad that build sensor hubs, camera interface modules and PMICs are where its adoption in India is concentrated. The practical constraint is rarely the specification; it is having bench instrumentation that can drive an I3C bus interactively during bring-up.
I3C Sensor Bring-Up with the Binho Supernova: Bus Scanning, Dynamic Addressing, CCC Commands, and IBI
I3C sensor bring-up is not an I2C bus scan with extra steps. Before the first register read you have to reset and run dynamic address assignment, read back each target's Provisioned ID, BCR and DCR, and configure events with CCCs. This guide walks that sequence on the Binho Supernova, which Binho specifies as an I3C Controller or Target at up to 12.5 MHz.
Binho Supernova: A Full MIPI I3C Exerciser for Firmware Teams
Binho specifies the Supernova for MIPI I3C spec versions v1.0, v1.1.1 and v1.2, up to 12.5 MHz, in SDR mode and HDR-DDR, with In-Band Interrupts, Hot-Join and all Common Command Codes, at 0.8 V to 3.3 V, and with an I3C role of Controller or Target. That combination is what makes interactive I3C bring-up practical on a bench rather than only on an FPGA prototype.
PCB Repair Guide: Detecting BGA Solder Joint Failures with VI Curve Analysis
How to use VI curve tracing to detect BGA solder joint failures, open balls, bridged pins, and cold joints, without X-ray equipment. A practical guide for Indian repair workshops.
DDR5 Signal Integrity Simulation with HyperLynx: Timing, Topology, and Compliance
DDR5 at 6400 MT/s demands pre-layout topology exploration and post-layout timing validation. Learn how HyperLynx SI helps semiconductor design teams in India simulate write leveling, DQ/DQS timing, and VrefDQ noise margins.
Signal Integrity for High-Speed PCB Design: A Practical Guide for Indian Hardware Teams
With DDR5, PCIe Gen5, and USB4, every multi-layer PCB is now a high-speed design. Here's how Indian hardware teams can avoid common signal integrity mistakes and ship boards that work on the first spin.
Total Phase Wins Best in Show at Embedded World North America 2025
We are proud to share that our principal partner Total Phase received the Best in Show award in the Test & Measurement category at Embedded World North…
AI-Assisted Code Remediation for Safety-Critical C and C++
Perforce has extended AI-assisted code remediation across both Helix QAC and Klocwork, delivered through a Static Analysis MCP server that Perforce describes as IDE-agnostic and Code-Assist tool-agnostic, with support for private, air-gapped environments. The fix is proposed by AI. The finding it is fixing still comes from the qualified analysis engine, and a developer approves every change.
FADOS 9F1 vs 7F1: Which Circuit Board Tester Is Right for Your Workshop?
A side-by-side comparison of the FADOS 9F1 and FADOS 7F1 circuit board testers, features, specifications, use cases, and which one fits your repair operation.
VI Curve Tracing Explained: How FADOS Finds PCB Faults Without Power
A practical guide to VI curve tracing, the power-off board diagnostic technique used by FADOS testers to find shorts, open circuits, and degraded components without schematics or powered test fixtures.
Siemens EDA User2User Forum 2026: Hyderabad
GSAS Micro Systems hosted the Siemens EDA User2User Forum 2026 at Westin Mindspace, Hitech City, Hyderabad, bringing together semiconductor design…
Calibre, Questa, and Tessent: Siemens IC Verification for the Indian Semiconductor Ecosystem
India's growing automotive semiconductor design activity, EV powertrain controllers, ADAS processors, battery management ICs, increasingly requires IS...
Siemens EDA User2User Forum 2026: Noida
GSAS Micro Systems hosted the Siemens EDA User2User Forum 2026 in Noida, bringing together IC design, verification, and implementation professionals from…
GSAS Micro Systems Partners with Siemens EDA for India Market
GSAS Micro Systems is now an official Siemens EDA (Siemens Digital Industries Software) partner in India, bringing the full suite of Siemens electronic ...
Keysight Cliosoft DDM Seminar
Keysight IP & Design Data Management Abstract: In today’s rapidly evolving technological landscape, efficient management of hardware/firmware ...
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