Calibre, Questa, and Tessent: Siemens IC Verification for the Indian Semiconductor Ecosystem

India’s semiconductor ambitions are no longer aspirational, they are operational. With major design centres in Bangalore, Hyderabad, Chennai, Pune, and Noida employing tens of thousands of IC design engineers, and ATMP (Assembly, Test, Mark, and Pack) facilities entering construction and qualification phases, India is building a semiconductor ecosystem that spans from RTL to packaged silicon.

But designing an IC is only part of the challenge. Verifying that the design is correct, functionally, physically, and for manufacturing test, is where the majority of the engineering effort and schedule risk resides. At advanced process nodes, verification is routinely the long pole in the schedule, and it is the stage where a missed defect converts directly into a respin.

Getting the verification infrastructure right is not optional. It is the difference between silicon that works on first tapeout and silicon that requires costly respins.

Siemens EDA provides the verification tools that the semiconductor industry relies on at every stage: Calibre for physical verification, Questa for functional verification, Tessent for design-for-test, and Solido for variation-aware analog design. This article examines each tool’s role and their integration across the IC design-to-manufacturing flow.

Calibre: The Foundry Standard for Physical Verification

Calibre is the physical verification platform that foundries certify and IC designers depend on. Its market position is not a matter of marketing, it is a matter of foundry requirements. When TSMC, Intel, GlobalFoundries, and other major foundries qualify a new process node, Calibre rule decks are among the first verification collateral they provide. Most foundry PDKs (Process Design Kits) include Calibre rule decks as the reference implementation.

Design Rule Checking (DRC)

Calibre DRC verifies that the physical layout conforms to the foundry’s manufacturing rules. At advanced nodes (7nm, 5nm, 3nm), the number of design rules has grown enormously, current rule decks contain thousands of individual rules covering minimum width, minimum spacing, enclosure, extension, density, and pattern-specific constraints that arise from the manufacturing process.

Calibre DRC handles this complexity through a hierarchical verification engine that processes the design at multiple levels of abstraction simultaneously. The tool exploits the repetitive structure of IC layouts, standard cells, memory arrays, I/O rings, to verify large designs efficiently. Run times that would be impractical with a flat verification approach become manageable through Calibre’s hierarchical and distributed processing capabilities.

Layout vs. Schematic (LVS)

Calibre LVS verifies that the physical layout implements the intended circuit. The tool extracts the circuit netlist from the layout geometry, compares it against the source schematic netlist, and reports any discrepancies: missing devices, extra devices, incorrect connections, and parameter mismatches.

At advanced nodes, LVS must handle not just the transistors and interconnect but also the parasitic devices that arise from the physical structure: well proximity effects, LOD (Length of Diffusion) effects, and stress-dependent mobility variations. Calibre LVS models these effects and reports them as part of the extracted netlist, ensuring that the post-layout simulation accurately represents the manufactured circuit.

Parasitic Extraction (xRC)

Calibre xRC extracts the parasitic resistance and capacitance of the interconnect from the physical layout. This extracted parasitic network is essential for post-layout timing analysis, signal integrity verification, and power analysis.

At advanced nodes, interconnect parasitics dominate circuit performance. Wire delay exceeds gate delay, and coupling capacitance between adjacent wires creates crosstalk that can cause functional failures. Calibre xRC provides the accuracy needed to model these effects, with extraction capabilities that scale from fast, reduced-order models for early analysis to full-detail extraction for final signoff.

PERC (Programmable Electrical Rule Check)

Calibre PERC verifies electrical reliability rules that go beyond DRC and LVS: electromigration limits, voltage-dependent spacing rules, ESD protection connectivity, latch-up prevention rules, and antenna effect checks. These rules address failure mechanisms that occur over the product lifetime rather than at initial test, making them critical for reliability-sensitive applications such as automotive and aerospace.

Questa One: Functional Verification

Questa is Siemens’ functional verification platform, and it has evolved a long way beyond the ModelSim legacy. Siemens has since consolidated the line under the Questa One brand: the former Questa hub URL now returns a 301 redirect to the Questa One page, and the ModelSim URL redirects to Questa One Sim. We cover that consolidation, the product family and the migration questions in detail in what happened to Questa Prime.

For Indian design teams evaluating or upgrading their verification infrastructure, understanding the capabilities that Questa One provides, and why they matter, is essential.

Performance

The figure Siemens publishes for Questa on its EDA AI page is a 3x reduction in verification coverage closure time and a 10x reduction in the verification of design changes. That is Siemens’ claim, and it is the only Questa performance multiplier we quote.

For Indian design teams running regression suites with thousands of test cases, coverage closure and re-verification after design changes are exactly the two costs that dominate the schedule, which is why those are the two numbers Siemens chooses to lead with.

Full SystemVerilog Support

Questa provides complete support for the SystemVerilog language, including the verification-specific features that modern verification methodologies require: constrained random stimulus generation, functional coverage, assertions (SVA), and the SystemVerilog DPI (Direct Programming Interface) for integrating C/C++ models.

This full language support is essential for Indian design teams adopting the Universal Verification Methodology (UVM), which is built on SystemVerilog and has become the industry standard for IC functional verification.

UVM Support and Debug

Questa includes native UVM support: UVM-aware debugging, transaction-level visibility, sequence debugging, and coverage analysis integrated into the verification environment. The UVM debug capabilities allow verification engineers to trace stimulus generation, monitor transaction flow through the testbench, and identify the root cause of failures at the transaction level rather than the signal level.

For Indian verification teams building UVM testbenches for complex SoCs, this debugging capability significantly reduces the time from failure observation to root cause identification.

Clock Domain Crossing (CDC) Analysis

Modern SoCs contain multiple clock domains, and errors at clock domain boundaries are among the most difficult bugs to find through simulation alone. Questa CDC provides static analysis of clock domain crossings, identifying potential metastability risks, missing synchronisers, and reconvergence issues.

CDC bugs are particularly insidious because they are timing-dependent and may not manifest in simulation but cause intermittent failures in silicon. Static CDC analysis catches these issues systematically, regardless of the simulation stimulus.

Tessent: Design for Test

Designing an IC that works is necessary. Designing an IC that can be tested in production is equally necessary. Tessent provides the DFT (Design for Test) infrastructure that enables efficient production testing at wafer sort and final test.

Scan Chain Insertion

Tessent automatically inserts scan chains into the design, converting sequential logic into a structure that can be controlled and observed during production test. The tool optimises scan chain architecture for test time, power consumption during scan (a critical concern at advanced nodes), and routing congestion.

Built-In Self-Test (BIST)

For embedded memories (SRAM, ROM, register files), Tessent provides memory BIST (MBIST) that generates on-chip test logic for production memory testing. The MBIST engine executes standard march algorithms and reports results through a compact test interface, eliminating the need for expensive memory test equipment.

For logic blocks, Tessent provides logic BIST (LBIST) that generates pseudo-random test patterns on-chip, reducing the dependence on external automatic test equipment for ongoing production testing.

Automatic Test Pattern Generation (ATPG)

Tessent ATPG generates the test patterns that are applied during production test to detect manufacturing defects. The tool targets stuck-at faults, transition faults, path delay faults, and bridging faults. On its EDA AI page Siemens publishes a 10x faster architecture implementation and 5x shorter test time for DFT with Tessent; achievable fault coverage itself depends on the design, the fault model, and the DFT architecture, so it is not a number any tool vendor can promise in the abstract.

At advanced process nodes, the relationship between test pattern quality and defect coverage becomes critical. A small improvement in fault coverage can represent a significant improvement in defect parts-per-million (DPPM), which directly affects product quality and customer returns.

ISO 26262 Automotive Compliance

For Indian automotive IC design teams, Tessent provides specific capabilities for ISO 26262 functional safety compliance. The tool generates diagnostic test patterns that achieve the fault metrics required by ASIL-B, ASIL-C, and ASIL-D safety integrity levels. This includes both in-system test (patterns that can be executed during vehicle operation for continuous safety monitoring) and production test (patterns for manufacturing defect screening).

India’s growing automotive semiconductor design activity, EV powertrain controllers, ADAS processors, battery management ICs, increasingly requires ISO 26262 compliance, making Tessent’s safety-aware DFT capabilities directly relevant.

Solido: Variation-Aware Design for Analog/Mixed-Signal

At advanced process nodes, manufacturing variation is not a secondary effect, it is a primary design constraint. Transistor threshold voltage, oxide thickness, interconnect dimensions, and doping concentrations all vary across the wafer and between wafers. Analog and mixed-signal circuits are particularly sensitive to these variations because their performance depends on device matching and absolute parameter values.

Monte Carlo Acceleration

Traditional Monte Carlo analysis, running thousands of simulations with randomly varied process parameters, is the standard approach for variation-aware design but is computationally expensive. Siemens describes Solido on its EDA AI page as delivering “2-1000X+ faster simulation, variation-aware design and verification, characterization and IP validation”. That range is Siemens’ own, and the spread in it is honest: the acceleration achieved depends heavily on the circuit and the sigma target.

The acceleration comes from intelligent sampling algorithms that focus simulation effort on the statistically significant regions of the parameter space, rather than uniformly sampling the entire space. The result is the same statistical confidence in the design margins but achieved in hours rather than weeks.

High-Sigma Analysis

For applications requiring extremely low failure rates, automotive, aerospace, medical, the design must be verified at high sigma levels (4-sigma, 5-sigma, or beyond). Traditional Monte Carlo analysis becomes impractical at these sigma levels because the number of required simulations grows exponentially. Solido provides high-sigma analysis techniques that efficiently explore the tails of the parameter distribution, identifying the specific combination of process variations that cause the design to fail.

For Indian IC design teams working on automotive and defence applications, high-sigma verification is not optional, it is a specification requirement.

Integration Across the IC Design Flow

The power of the Siemens IC verification portfolio lies not just in the individual tools but in their integration across the design-to-manufacturing flow.

The design starts with RTL, which is verified by Questa for functional correctness. The verified RTL is synthesised and placed-and-routed, producing a physical layout. Tessent inserts DFT structures during or after synthesis, and the test patterns are generated and validated.

Calibre verifies the physical layout for manufacturing rules (DRC), circuit correctness (LVS), and parasitic extraction (xRC). Solido verifies the analog blocks for variation robustness. The verified design goes to tapeout, and the Tessent test patterns go to the production test floor.

At each stage, the tools share data: Questa simulation results inform Tessent test pattern validation, Calibre extracted parasitics feed back into Questa for post-layout verification, and Solido variation analysis identifies the process corners that Questa must simulate.

Indian Context: Building Verification Infrastructure

India’s semiconductor ecosystem is at an inflection point. The design talent is established, Indian design centres produce IC designs across digital, analog, and mixed-signal domains. The manufacturing infrastructure is under construction, with ATMP facilities progressing toward qualification.

What the ecosystem needs now is production-ready verification infrastructure: the tools, methodologies, and expertise to take designs from concept through tapeout with first-silicon success. This is not just a tool procurement decision, it is an infrastructure investment that determines the productivity of the design teams and the quality of the silicon they produce.

For Indian IC design teams, whether at established multinationals, growing startups, or government research laboratories, the Siemens verification portfolio provides the capabilities that the foundries certify, that the methodologies require, and that production quality demands.

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Ready to evaluate Siemens IC verification tools? Contact GSAS Micro Systems for tool evaluation, methodology consultation, and deployment planning for Calibre, Questa, Tessent, and Solido. We work with Indian semiconductor design teams to establish verification infrastructure that delivers first-silicon success. Reach us at gsasindia.com/contact.