AI and Complexity Are Redrawing EDA: Siemens on the Trillion-Transistor Era

Siemens published a piece on 10 September 2026 arguing that semiconductor complexity has moved past what traditional design methods handle, and that electronic design automation has to change shape in response. The argument is made at length in an episode of the Industry Forward Podcast, which we have embedded below.

Listen to the episode

Host Dale Tutt, Vice President of Industry Strategy at Siemens Digital Industries Software, is joined by Ankur Gupta, Executive Vice President of EDA Integrated Circuit Software at Siemens EDA, who oversees the company’s integrated circuit design portfolio.

The argument, in short

Siemens’ position is that industrial AI and rising compute demand are driving complexity faster than design methodology has kept up. In their words, “Industrial AI and growing compute demand are contributing to accelerating semiconductor complexity”, and as “transistor counts race toward one trillion per chip, the tools and workflows that engineers rely on must evolve to keep pace.”

The sharper claim is about where design boundaries sit. Gupta describes a world where “Things are interconnected at a different level” and “it’s just this massively interconnected world”. Traditional EDA, he argues, operated in “a siloed environment”, and “It’s no longer possible to draw those lines.”

All of the above is Siemens’ framing and Siemens’ wording. The trillion-transistor figure is their projection, not a GSAS forecast.

What it means if you are designing in India

Strip away the scale of the numbers and the practical consequence is about where verification happens, and it applies well below the leading edge.

The silo was never a physical fact, it was a convenience. Chip, package and board were designed separately because the interactions between them were small enough to ignore, or to fix late with a respin. As speeds rise and margins shrink, those interactions stop being ignorable. A DDR5 interface is not a board problem or a silicon problem; it is both, and the failure shows up at integration.

The cost of finding it late is what changes. For a team in India shipping a product rather than a research part, the expensive event is not a complex chip. It is a prototype spin discovered to be non-functional for a reason that was visible in simulation, had anyone simulated across the boundary.

This is a methodology question before it is a tools question. Buying a system-level tool does not create a system-level process. The teams that benefit are the ones that change when verification happens, not just what software performs it.

Where this touches our portfolio

We represent Siemens EDA, formerly Mentor Graphics, in India. The tools that live at exactly the boundary Gupta describes are the ones where chip meets board:

• HyperLynx for signal integrity, power integrity and electrical design rule checking, which is where pre-layout topology exploration and post-layout verification happen
• Xpedition for the PCB design flow itself, including the ECAD and MCAD co-design that the podcast’s interconnection argument points toward

If you want to see how the flow fits together before committing, our Siemens EDA partner page carries an interactive tour, and there is a free 30-day trial of Xpedition Standard.

Where GSAS fits

GSAS Micro Systems is an engineering partner for Siemens EDA in India, with field engineers supporting design teams in Bengaluru, Hyderabad, Chennai, Pune, Mumbai and Delhi NCR. Our work on this is the practical end: helping teams decide which verification belongs early, which tier of tooling their programme actually needs, and how to migrate a flow without stopping work.

To talk it through, ask an engineer a question or request a quote.

Sources: Siemens Digital Industries Software, AI and complexity drive new era in EDA, 10 September 2026 and the Industry Forward Podcast episode