Binho Supernova: A Full MIPI I3C Exerciser for Firmware Teams

MIPI Alliance lists I3C v1.0 as a 2016 release, yet adoption on real hardware has lagged behind the specification’s ambition. Part of the reason is tooling: a bus standard needs controller silicon, target silicon and instruments that can drive it, and the third arrived last. Engineers designing I3C sensor hubs, camera modules, and power management ICs had to rely on FPGA-based prototypes or silicon vendor evaluation boards to generate I3C traffic, neither of which provides the interactive, scriptable bus access that firmware bring-up demands.

The Binho Supernova is a USB-connected I3C exerciser built to close that gap. Binho specifies support for MIPI I3C spec versions v1.0, v1.1.1 and v1.2, speeds up to 12.5 MHz, both SDR mode and HDR-DDR, and In-Band Interrupts, Hot-Join and all Common Command Codes, at an I3C signalling range of 0.8 V to 3.3 V.

I3C Fundamentals the Supernova Exercises

I3C introduces several bus mechanisms that have no equivalent in I2C, and the Supernova implements all of them as first-class operations.

Dynamic Address Assignment (DAA) eliminates the hardcoded 7-bit slave addresses that cause I2C bus conflicts when multiple identical sensors share a bus. The Supernova, acting as I3C controller, assigns addresses to targets at runtime using the ENTDAA (Enter Dynamic Address Assignment) Common Command Code. Engineers can enumerate all targets on the bus, inspect their BCR (Bus Characteristics Register) and DCR (Device Characteristics Register), and assign addresses interactively through Mission Control or programmatically through the Python SDK.

In-Band Interrupts (IBI) replace the dedicated IRQ lines that I2C sensors require. An I3C target can assert an interrupt directly on the SDA line during the bus idle phase, and the Supernova captures these IBIs with full payload data and nanosecond timestamps. For teams designing sensor hubs that aggregate data from multiple accelerometers, gyroscopes, or environmental sensors, IBI support on the exerciser is essential for validating the interrupt arbitration behavior before committing to silicon.

Hot-Join allows I3C targets to connect to the bus after the controller has already completed initial enumeration. The Supernova detects hot-join requests and walks through the join handshake, a feature critical for modular systems where sensor boards are plugged in at runtime, such as industrial I/O modules or medical instrument cartridges.

Controller or Target role. Binho lists the Supernova’s I3C role as “Controller or Target”. Most of this article assumes the controller direction, which is the common case, but the target direction is the one that lets a team exercise a controller implementation from the other side of the bus. We cover it separately in running the Binho Supernova as an I3C target.

HDR-DDR: Doubling I3C Throughput

Standard Data Rate (SDR) mode operates I3C push-pull signalling at up to 12.5 MHz, already faster than I2C’s 3.4 MHz high-speed mode. But for bandwidth-hungry applications like camera sensor configuration or audio codec streaming, the Supernova supports HDR-DDR (High Data Rate, Double Data Rate) mode, which transmits data on both the rising and falling clock edges, effectively doubling throughput at the same clock frequency.

Binho lists HDR-DDR support for the Supernova across spec versions v1.0, v1.1.1 and v1.2. The Supernova generates HDR-DDR traffic from both Mission Control and the SDK, allowing engineers to validate that their I3C target devices correctly enter and exit HDR mode, handle the HDR framing protocol, and maintain data integrity at double data rate.

Beyond I3C: I2C, SPI, UART and GPIO

The Supernova is not solely an I3C tool. Binho specifies a 50 MHz SPI controller with up to four chip-select signals and all four SPI modes, a 1 MHz I2C controller with configurable pull-ups, 7-bit addressing and clock stretching, UART at 115200 baud with hardware flow control, and six dedicated configurable GPIO pins. Those pins run at 1.2 V to 3.3 V, while the I3C domain reaches down to 0.8 V.

The 50 MHz SPI controller makes the same instrument capable of high-speed flash programming alongside I3C target validation, and the 1 MHz I2C controller covers the mixed-bus designs that are the normal state of affairs during migration, where some devices remain on I2C while others move to I3C.

Software: Mission Control and SDKs

Mission Control is the cross-platform GUI application (Windows, macOS, Linux) that provides interactive I3C bus exploration. From Mission Control, engineers can scan the bus for targets, read device characteristic registers, execute CCC sequences (ENTDAA, SETDASA, GETMWL, GETMRL, ENEC, DISEC, and others), send private read/write transfers, and monitor bus traffic in real time. The GUI is the fastest path from unboxing to first I3C transaction.

For automated testing and production workflows, Binho ships a Python SDK with Jupyter examples plus C, C++ and C# SDKs, providing programmatic control over I3C, I2C, SPI, and UART transactions. Teams can script I3C target validation suites that run as part of CI/CD pipelines, build production test fixtures that verify I3C connectivity before board shipment, and create regression test benches that catch silicon errata or firmware regressions in I3C target implementations.

Who Needs the Supernova

The Supernova is the right tool for engineering teams designing or integrating I3C targets, sensor IC teams validating their I3C peripheral implementation, SoC teams bringing up I3C controller IP, system integrators connecting I3C sensors to application processors, and test teams building I3C validation fixtures for production. It is also the appropriate Binho instrument for teams that need SPI speeds above the Binho Nova’s 12 MHz ceiling, as its 50 MHz SPI capability covers high-speed flash programming and SPI display driving without requiring a separate instrument.

Why Buy from GSAS

GSAS Micro Systems is an authorized engineering partner in India, providing the Supernova with INR invoicing, evaluation unit programs, and I3C protocol expertise. Our applications engineers support MIPI I3C target bring-up, HDR-DDR mode testing, CCC sequence development, and Mission Control deployment, helping embedded teams across India adopt I3C with confidence. Contact GSAS from offices in Bengaluru, Hyderabad, Chennai, Pune, Mumbai, and Delhi NCR for evaluation units and technical guidance on integrating the Supernova into your I3C development workflow.