Calibre

Calibre is the IC physical verification and signoff platform from Siemens EDA. It provides the verification engines that ensure a chip layout is manufacturable and electrically correct before committing to silicon fabrication. Calibre’s certified rule decks from TSMC, Samsung, Intel, and GlobalFoundries are the definitive reference for tapeout signoff at advanced process nodes down to 2nm.

The platform encompasses the full spectrum of physical verification: design rule checking (DRC) validates geometric compliance with foundry manufacturing rules, layout vs. schematic (LVS) confirms that the physical layout matches the intended circuit netlist, and parasitic extraction (xRC) generates accurate RC netlists for post-layout timing and signal integrity simulation. Calibre Pattern Matching identifies and classifies layout constructs that impact yield or reliability, while PERC (Programmable Electrical Rule Checking) catches ESD, latch-up, and electrical reliability violations that geometric DRC cannot detect.

Calibre is essential for any IC design team targeting volume production at advanced foundry nodes, where hundreds of thousands of design rules must be satisfied for successful tapeout. Analog, digital, mixed-signal, RF, and memory designs all rely on Calibre for final signoff verification.

GSAS Micro Systems provides Calibre licensing, deployment, and technical support for semiconductor design teams across India, with assistance for foundry rule deck setup, verification flow integration, and custom rule development.