Tessent
IC VerificationTessent from Siemens EDA: design-for-test (DFT) insertion, ATPG and test compression, memory and logic BIST, diagnosis and yield learning, and silicon lifecycle solutions for automotive and high-reliability ICs. Available in India from GSAS.
ATPG and compression
Tessent FastScan, TestKompress, ScanPro
Hierarchical DFT
Tessent Platform, Streaming Scan Network (SSN), RTL Pro
BIST
Tessent MemoryBIST, LogicBIST, In-System Test, MissionMode
Test access
IEEE 1149.1 BoundaryScan, IEEE 1687 IJTAG, IEEE 1838 multi-die
Diagnosis
Tessent Diagnosis, YieldInsight, SiliconInsight
Safety
ISO 26262 tool certification for each release (per Siemens)
Overview
About Tessent
![]()
Tessent is the Siemens EDA family of design-for-test (DFT) and silicon lifecycle tools. It puts test structures into a chip during design, generates the patterns that test it in manufacturing, diagnoses the parts that fail, and keeps testing and monitoring the chip after it ships.
Siemens describes Tessent Silicon Lifecycle Solutions as helping teams “deliver a faster time to market by reducing design complexity using high-quality DFT,” with “advanced debug, safety & security features and in-life data analytics.” GSAS Micro Systems supplies Tessent in India with local application engineering for DFT flow integration, automotive safety and production test.
The Four Tessent Solution Areas
Siemens organises Tessent into four solution areas. Each one maps to a stage of a chip’s life.
| Solution area | Stage | What it covers |
|---|---|---|
| Tessent Advanced DFT (Test) | Design and manufacturing test | Logic and memory test, scan insertion, ATPG, compression, BIST, IEEE test access |
| Tessent Yield Learning | Production ramp | Diagnosis of failing parts, systematic defect identification, silicon bring-up |
| Tessent Safety and Security | In-field operation | In-system test, fault grading, ISO 26262 support, security across the lifecycle |
| Tessent Embedded Analytics | Validation and deployment | On-chip functional monitoring, trace and debug, including RISC-V |
Tessent Advanced DFT: Test Structures and Patterns
This is where most DFT engineers spend their time. Siemens lists the following products under Tessent Test Solutions:
| Product | What Siemens says it does |
|---|---|
| Tessent TestKompress | Deterministic scan test “using patented on-chip compression to reduce test data volume and cut test time” |
| Tessent FastScan | ATPG that can be “applied to most any type of design” to generate high-coverage, compact test sets |
| Tessent ScanPro | Scan insertion, hierarchical DFT and logic BIST readiness |
| Tessent Streaming Scan Network (SSN) | Decouples core-level and chip-level DFT requirements to cut DFT development time and test cost |
| Tessent Platform | Automation of the Tessent flow for hierarchical DFT |
| Tessent RTL Pro | Software to streamline a broad range of DFT tasks for IC design teams |
| Tessent MemoryBIST | Test, repair, debug and characterisation of embedded memories |
| Tessent LogicBIST | Logic built-in self-test for safety-critical ICs such as automotive and medical |
| Tessent In-System Test | Applies deterministic test patterns in-system, as an alternative to traditional logic BIST |
| Tessent MissionMode | IC test and diagnosis at any point during a vehicle’s functional operation |
| Tessent BoundaryScan | IEEE 1149.1 boundary scan insertion |
| Tessent IJTAG and IJTAG Pro | IEEE 1687 instrument integration and faster IJTAG pattern loading |
| Tessent Multi-die | IEEE 1838-compliant test access for 3D stacked ICs |
| Tessent AnalogTest | Analog test pattern development and verification |
| Tessent DefectSim | Transistor-level defect simulation for analog, mixed-signal and non-scan circuits |
Streaming Scan Network for large SoCs and chiplets
For large SoCs built from many cores, the hard part of DFT is getting scan data to every core without the chip-level test architecture dictating every core’s design. Siemens describes Tessent SSN as eliminating “the difficult and costly trade-offs between test implementation effort and manufacturing test cost by decoupling core-level and chip-level DFT requirements.” Siemens’ Tessent Test Solutions page notes that SSN won the Siemens Innovator of the Year 2022 award for Outstanding Invention.
Tessent for Automotive: ISO 26262 and In-System Test
Automotive ICs must be tested not only in the factory but during the vehicle’s life, to catch latent faults. Siemens’ Tessent Safety and Security pages state:
- ISO 26262 tool certification: “for each release there is an ISO 26262 certification that ensure the tools are suitable for use with Automotive projects.”
- BIST as a safety mechanism: “Both Memory BIST and Logic BIST are great technologies to use as a safety mechanism, as they provide extremely high diagnostics coverage with minimal area.”
- In-field test: the MissionMode in-system test controller lets teams run system tests in many different scenarios while the device is in its target application.
Siemens introduced Tessent In-System Test on 5 November 2024, describing it as working with Tessent SSN so customers can “apply embedded deterministic test patterns in-system throughout a product’s lifecycle.” Patterns generated with Tessent TestKompress are applied through standard APB or AXI bus interfaces. Siemens names automotive, aerospace and medical devices as the industries where this matters most.
Tessent Yield Learning: Diagnosis After Manufacturing
When parts fail production test, the question becomes why. Siemens lists three tools:
- Tessent Diagnosis applies “layout-aware and cell-aware diagnosis technologies to accurately classify and identify the location of defects causing failures during manufacturing tests.”
- Tessent YieldInsight removes noise from diagnosis data to find systematic yield limiters and pick the best devices for failure analysis.
- Tessent SiliconInsight speeds test bring-up, debug and silicon characterisation of devices that contain Tessent test structures.
Tessent Embedded Analytics
Siemens describes Tessent Embedded Analytics as functional monitoring that enables “processor and system-wide trace and debug in real-time and post-deployment analytics for complex System-on-Chips.” It includes Tessent UltraSight-V for RISC-V debug and trace, and Tessent UltraSight for wider SoC monitoring. Siemens states the solution is processor-agnostic.
Who Uses Tessent in India
- SoC and ASIC DFT teams inserting scan, compression and BIST and generating ATPG patterns before tapeout.
- Automotive semiconductor teams that need ISO 26262 in-system test and fault grading.
- Product and test engineering teams diagnosing production failures and ramping yield.
- RISC-V and SoC validation teams that need on-chip trace and debug.
How GSAS Supports Tessent Teams in India
GSAS Micro Systems is an authorized Siemens EDA partner in India and a value added distributor/reseller for Siemens EDA products. We have a dedicated FAE team ready to help you with custom built solutions matching your needs. Our application engineers work with DFT and test teams in Bengaluru, Hyderabad, Chennai, Pune, Mumbai and Delhi NCR on:
- DFT flow integration: fitting Tessent into your synthesis and implementation flow.
- Automotive safety: planning in-system test and BIST as safety mechanisms for ISO 26262 programmes.
- Production test: pattern generation, test time reduction and diagnosis set-up.
- Licensing and procurement: INR quotes with GST invoicing for the Tessent configuration your flow needs.
Tessent works alongside other Siemens IC tools we supply: Questa One, whose Sim DX engine accelerates DFT pattern verification with Tessent and whose Sim FX engine handles fault simulation, and Calibre for physical signoff. See the full Siemens EDA partner page.
References
- Siemens, Tessent Silicon Lifecycle Solutions
- Siemens, Tessent Test Solutions
- Siemens, Tessent Safety and Security
- Siemens, Tessent Yield Learning
- Siemens, Tessent Embedded Analytics
- Siemens press release, Siemens’ Tessent In-System Test software enables advanced, deterministic testing throughout the silicon lifecycle, 5 November 2024
Blog
Siemens EDA Insights
Emulation vs FPGA Prototyping vs Simulation for SoC Teams
Simulation, hardware emulation and FPGA prototyping each answer a different pre-silicon question. A plain explainer for Indian SoC and ASIC teams on what each one is for, how they trade visibility against speed, and how Siemens' Veloce CS line divides the hardware side.
HyperLynx Agentic Toolkit: What It Means for India
Siemens has announced the HyperLynx Agentic Toolkit: an orchestration agent and specialised SerDes, DDR, SI and PI agents that run HyperLynx simulations from natural-language goals. What Siemens announced, when it is planned, and what Indian SI/PI teams can do now.
Siemens EDA Customer Results: 10 Published Case Studies
Ten customer stories Siemens has published on Xpedition, HyperLynx, Valor NPI and Calibre, from Leonardo and TESAT to Mindray, FANUC and ETRI with Amkor: who they are, which Siemens tools they used, and the result in Siemens' own words.
Related products
More from Siemens EDA
All Siemens EDA products →
Innovator3D IC Layout
TSMC InFO-certified IC packaging layout tool for 2.5D/3D integration and advanced fan-out wafer-level packaging. Buy in India from GSAS with local support.
View Innovator3D IC Layout →
Xpedition Package Designer
IC package substrate and interposer layout for BGA, flip-chip, fan-out, and 2.5D/3D heterogeneous integration. Available in India from GSAS.
View Xpedition Package Designer →
Calibre
IC physical verification and signoff platform from Siemens EDA: DRC, LVS, parasitic extraction, PERC reliability checking and DFM for tapeout. Available in India from GSAS.
View Calibre →FAQ
Common questions about Tessent
What is Tessent?
Are the Tessent tools ISO 26262 certified?
What is the difference between Tessent TestKompress and Tessent FastScan?
What is Tessent Streaming Scan Network (SSN)?
Is Tessent available in India?
Interested in Tessent?
Get pricing, an evaluation unit, or a technical consultation from our application engineers.