Xpedition Package Designer

Xpedition Package Designer from Siemens EDA is a dedicated IC package substrate and interposer layout tool that handles the full complexity of modern semiconductor packaging, from conventional wire-bond and BGA packages through advanced flip-chip, fan-out wafer-level, and 2.5D/3D heterogeneous integration technologies. As the semiconductor industry shifts toward chiplet architectures and advanced packaging to extend Moore’s Law, the package substrate has become as complex as a high-density PCB, requiring specialized design tools with IC-scale routing density and PCB-scale manufacturing awareness.

The tool provides die placement, bump and ball assignment, redistribution layer (RDL) routing, via structure definition, and design rule checking for multi-layer package substrates. It supports the full range of packaging technologies: traditional wire-bond and QFN packages, flip-chip BGA with high-density escape routing, fan-out wafer-level packaging (FOWLP), and advanced 2.5D interposer designs such as TSMC CoWoS and InFO. For chiplet-based designs, Xpedition Package Designer handles multi-die placement and routing on silicon interposers and organic substrates with heterogeneous die integration.

The package-to-board co-design workflow with Xpedition PCB enables concurrent optimization of package pin-out and board routing, while the mechanical co-design workflow with NX provides warpage simulation and thermo-mechanical stress analysis for reliability prediction. This integrated approach is critical for advanced packages where package and board design decisions are tightly coupled.

GSAS Micro Systems provides Xpedition Package Designer licensing and technical support for semiconductor packaging teams across India, with guidance on advanced packaging flow setup, co-design methodology, and foundry packaging technology integration.

Buy Xpedition Package Designer in India: GSAS India-Wide Support

GSAS provides Xpedition Package Designer with INR invoicing, local FAE support, and Siemens maintenance and support across India:

• Bengaluru: Semiconductor design centres working on BGA and flip-chip substrate layout for mobile SoCs, AI accelerators, and HBM integration for data centre chips
• Hyderabad: Defence semiconductor packaging teams designing multi-chip modules for radar and EW processors, and fabless companies outsourcing advanced package substrate design
• Chennai: Automotive semiconductor packaging for ADAS SoCs and sensor fusion ICs requiring package-to-board co-design with thermal management
• Pune: Automotive IC packaging R&D for powertrain and BMS controllers, and industrial semiconductor companies designing SiP modules
• Mumbai: Semiconductor packaging teams supporting telecom infrastructure ICs and data centre accelerator programs with 2.5D interposer substrates
• Delhi NCR: Defence and space semiconductor groups designing radiation-hardened packages, and telecom IC packaging for 5G RF front-end modules
• Coimbatore: Industrial power management IC packaging teams designing QFN and BGA substrates for motor drive and power conversion applications
• Visakhapatnam: Naval defence electronics packaging teams designing multi-chip modules for sonar processors, and medical device IC packaging
• Vadodara: Power semiconductor packaging teams designing high-current substrates for industrial power modules
• Kolkata: Eastern India semiconductor design teams and academic packaging research groups

Contact sales@gsasindia.com or call +91 80 6590 1783 for evaluation licenses, co-design flow setup, and advanced packaging methodology workshops.