zedboard

ZedBoard FPGA-in-the-Loop: HDL Verifier vs HDL Coder

Teams asking for FPGA-in-the-Loop on a ZedBoard usually name HDL Coder and SoC Blockset. FIL is actually HDL Verifier. Here is the correct product split, the JTAG versus Ethernet decision, and the 2015-era advice that is still sending Indian teams down the wrong path.