Siemens EDA: Turning Shift-Left from Slogan to Reality

What’s covered

Turning Shift-Left from Slogan to Reality is a free Siemens EDA webinar on Tuesday, November 10, 2026 at 10:30 PM IST, presented by Stuart Swan, on using SystemC models built with the open-source MatchLib library and synthesized with Catapult HLS as an early, throughput-accurate model that the RTL is then generated from.

SoC teams are told to shift left, to find design and verification problems early where they are cheap to fix. The reason it stays a slogan is structural: in most flows the first model that is both performance-accurate and authoritative is the RTL, and the RTL arrives late and simulates slowly. Everything earlier is either not accurate enough to trust or not the thing that gets built.

This session argues that SystemC models built with MatchLib and synthesized with Catapult HLS close that gap, because they exist early, simulate 30x to 100x faster than RTL, are throughput-accurate with respect to the final implementation, and are the actual source the RTL is generated from rather than a separate artefact that can drift.

What you will learn:

• Why shift-left has stayed a slogan in most SoC flows, and the four things an early model has to deliver before that changes
• How the usual modelling approaches, spreadsheets, untimed C++, TLM virtual platforms and hand-written RTL, measure against those four requirements and where each falls short
• How MatchLib makes a pre-HLS SystemC model tell the truth about system performance, and why throughput accuracy is close enough to cycle accuracy to sign off on
• How to move most functional verification and debug ahead of RTL, reusing the same UVM or SystemC testbenches you will later run on the RTL
• How one model becomes a single source of truth for architects, designers, verification, algorithm and software teams
• How teams adopt this incrementally alongside existing RTL, and what it looked like on real silicon in NVIDIA’s 87M-transistor ML SoC
• How MatchLib is being standardized in the Accellera Synthesis Working Group

Who should attend

• Hardware architects and design engineers
• Hardware design verification engineers
• EDA methodology engineers
• SoC design managers

Why the source model matters more than the speed

The 30x to 100x simulation speed-up is the headline, but it is not the structural argument. A fast model you maintain alongside the RTL is a second thing to keep in sync, and it diverges. The claim here is different: the SystemC model is the source, and the RTL is its output, so there is only one description of the design and no synchronisation problem to lose.

That is also what makes the early verification reusable rather than throwaway, since the same UVM or SystemC testbench runs against the model and later against the generated RTL.

Speakers

Stuart Swan is an HLS Technologist on the Catapult team, focusing on SoC modeling for High-Level Synthesis. He is co-author of the first book on SystemC, System Design with SystemC, and was IEEE technical chairman of the 2005 SystemC LRM. He worked at Qualcomm and Cadence before Siemens EDA.

Session time

Registration and attendance is free, and the session runs one hour. Time, speaker and abstract sourced from the official ON24 registration page.

Why GSAS is sharing this

GSAS Micro Systems is an authorized Siemens EDA engineering partner in India (formerly Mentor Graphics), across the IC and board portfolios. Indian SoC teams carry the same structural problem this session addresses: verification capacity is planned around an RTL that lands late, and the schedule has no slack to absorb it.

If your team is evaluating high-level synthesis, or wants the architecture and verification work to start before RTL exists, talk to us.

Register on ON24 →