Skip to main content

Designing PCBs for Edge AI: DDR, PCIe and HDI

Part 3 of 5

Edge AI Hardware: Density and Speed on One Board

Constraint-driven DDR and PCIe routing, and microvia breakout under the SoC.

Designing PCBs for Edge AI: DDR, PCIe and HDI, register to attend Save Your Seat →
Free registration
Date
Thursday, 17 December 2026
Format
Online, live webinar
Speakers
Ranjith Kumar Jadam, Sampath Radha Krishna & Bhavana Deevi (GSAS)
Cost
Free

Registration for Designing PCBs for Edge AI: DDR, PCIe and HDI is free and open online. Select Save Your Seat, or click the event image, to sign up.

Add to calendar Google Outlook.com Outlook 365 Apple / .ics

Edge AI puts compute, memory and camera links onto small boards, so density and speed rise together. Part 3 covers stackup and impedance, constraints defined before routing, length and phase matching, and BGA breakout with microvias, all live in Xpedition.

This is Part 3 of 5 in the GSAS EDA Insights Series Webinars, PCB Design edition. Every session uses the same edge AI board, designed in Siemens Xpedition for the series, and includes a live demo.

What’s covered

  • Stackup and impedance set up before routing starts.
  • DDR constraints from a template, and one LPDDR4 byte lane routed and tuned.
  • A PCIe differential pair routed live.
  • Microvia fanout under the SoC and plane generation.

Who should attend

PCB layout and hardware design engineers working on high-speed or high-density boards, and design leads planning edge AI products.

Session time

ItemDetail
DateThursday 17 December 2026
Time3:30 to 4:30 PM IST
Format50 minutes of presentation and live demo in Siemens Xpedition, then 10 minutes of Q&A
CostFree, registration required
RecordingSlides and recording emailed to all registrants after the session

Ranjith Kumar Jadam, Technical Director and Solution Architect, presents with Sampath Radha Krishna and Bhavana Deevi, Field Application Engineers. All three are from GSAS.

The full series

  1. AI in PCB Design: What Works Today and How Reliable It Is, Thu 3 Dec
  2. Why PCBs Respin and How to Stop It: Checks During Design, Thu 10 Dec
  3. Designing PCBs for Edge AI: DDR, PCIe and HDI (this session)
  4. Multi-Board Systems: Rigid-Flex and ECAD-MCAD Co-Design, Thu 7 Jan
  5. Moving from Altium or KiCad to Xpedition: What Transfers and What Changes, Thu 14 Jan

Each part has its own registration. Can’t make it live? Register anyway and we will send you the slides and the recording. For an overview of all five parts, see the series announcement.

Evaluating Xpedition for your team?

GSAS Micro Systems is a value added distributor/reseller for Siemens EDA in India, with a dedicated FAE team. Features vary by Xpedition edition and add-on, and GSAS can map each demo to the edition it needs. Talk to us about Xpedition Standard, Xpedition Advanced, Xpedition Enterprise or a guided evaluation for your project. Talk to our team.

Register for Designing PCBs for Edge AI: DDR, PCIe and HDI

You will receive a confirmation email with your joining link. Form not loading? Open the registration page.

Frequently asked questions

When is Designing PCBs for Edge AI: DDR, PCIe and HDI, in IST?
Thursday 17 December 2026, 3:30 to 4:30 PM IST. The presentation and live demo run 3:30 to 4:20 PM, and questions run 4:20 to 4:30 PM.
Do I need to register for each part of the series separately?
Yes. Each of the five parts has its own registration. Register for every part you want to attend. You receive a confirmation email with the joining link for each one.
Can I get the recording if I can't attend live?
Yes. Register anyway. After the session we email the slides and the recording to everyone who registered, whether or not they attended.
Who presents this session?
Ranjith Kumar Jadam, Technical Director and Solution Architect, with Sampath Radha Krishna and Bhavana Deevi, Field Application Engineers. All three are from GSAS Micro Systems, Siemens EDA partner in India.