Arm MPS2+ FPGA Prototyping Board

The Arm MPS2+ (V2M-MPS2+) is the Cortex-M Prototyping System from Arm’s Versatile Express family, designed for evaluation and prototyping of Arm Cortex-M class processors and user peripherals. Built around an Altera Cyclone V FPGA, the board supports encrypted FPGA images for Cortex-M0, M0+, M1, M3, M4, and M7, and the SSE-100 and SSE-200 reference subsystems that pair these cores with CMSDK peripherals for system-level evaluation.

FPGA part-number note (2026-05-12): the previously published FPGA part identifier (5CEBA9F31C8N, ~300K LE) is more consistent with the original MPS2 board than the MPS2+. Verify against Arm’s current MPS2+ TRM before relying on the specific part identifier in procurement; the supported core list and the SSE-100/200 subsystem coverage are unchanged.

The board provides 8 MB of high-speed ZBT (Zero Bus Turnaround) SSRAM across four 2 MB banks with 64/32/32/16-bit interfaces, plus 16 MB of PSRAM for larger data storage. Peripherals include Ethernet (SMSC9220), audio codec, SPI connector, QSVGA touchscreen panel, 4-bit RGB video output, and multiple clock options including local PLL with programmable frequencies.

Technical Specifications

Feature	Specification
FPGA	Altera Cyclone V 5CEBA9F31C8N
Logic Elements	~300,000
FPGA Encryption	Supported (encrypted Cortex-M images)
ZBT SSRAM	4x 2 MB banks (64/32/32/16-bit) = 8 MB total
PSRAM	16 MB
Ethernet	SMSC9220 controller
Audio	AC97-compatible codec
Video	4-bit RGB output from motherboard
Display	QSVGA touchscreen panel
SPI	SPI connector for user peripherals
Clocks	Local PLL, multiple clock options
User I/O	8 LEDs, 8 DIP switches, 2 push buttons
Expansion	3x IDC expansion ports, IDC/LCD expansion port
Board Controller	MCC (STM32-based), microSD configuration
Debug, JTAG	Arm JTAG, 20-pin IDC JTAG, Mictor38
Debug, Cortex	20-pin Cortex debug + ETM, 10-pin Cortex debug
Debug, Trace	ARM 16-bit parallel trace
Debug, FPGA	ILA connector for Signal-TAP / Identify
Configuration	Fast programming < 1 min, re-config < 10 sec
Part Number	V2M-MPS2-0318C

Supported Cortex-M Processors

The MPS2+ ships with fixed M-class application notes and supports:

Processor	Architecture	Key Feature
Cortex-M0	Armv6-M	Smallest Cortex-M, low gate count
Cortex-M0+	Armv6-M	Energy-efficient, single-cycle I/O
Cortex-M1	Armv6-M	FPGA-optimized Cortex-M
Cortex-M3	Armv7-M	Hardware multiply/divide, MPU
Cortex-M4	Armv7E-M	DSP extensions, optional FPU
Cortex-M7	Armv7E-M	Superscalar, cache, TCM

A Cortex-M0 design start example is included with CMSDK peripherals. Quartus II example design files are provided for FPGA customization. A licence is required to edit Arm IP designs.

MPS Board Comparison

Feature	MPS2+	MPS3	MPS4
FPGA	Altera Cyclone V (300K LE)	Xilinx Kintex UltraScale	AMD Virtex UltraScale+ (3.8M LE)
Processor Support	Cortex-M (incl. SSE-100/200)	Cortex-M, A, R (incl. Corstone-300/310)	Cortex-A, R, M (incl. Corstone-315/320)
Memory	8 MB SSRAM + 16 MB PSRAM	4 GB DDR4 + 16 GB eMMC	16 GB DDR4 + 128 MB QSPI
Expansion	IDC ports, SPI	FMC-HPC + Arduino + Pmod	FMC+ + Arduino + Pmod + PCIe
Best For	Cortex-M evaluation	Complex SoC prototyping	AI/ML + next-gen silicon

Why GSAS for MPS2+

GSAS provides MPS2+ FPGA prototyping boards in India with manufacturer warranty and local support. The MPS2+ is used by SoC design teams evaluating Cortex-M IP, software teams developing firmware ahead of silicon, and university labs teaching Arm architecture. Our team assists with FPGA image selection, ZBT memory configuration, debug probe setup, and Keil MDK / Arm Development Studio integration. For more advanced prototyping, see the MPS3 and MPS4.