Siemens EDA: What's New in HyperLynx 2610

What’s covered

What’s new in HyperLynx 2610 is a free Siemens EDA webinar on Thursday, October 22, 2026 at 9:30 PM IST, presented by Sajeda Tamimi and Kirk Fabbri. Registration is free.

This is a release deep dive rather than an introduction. Siemens describes it as a comprehensive walk through the HyperLynx 2610 release and how the updates change the high-speed design and verification phase.

The session spans signal integrity, power integrity and the DRC and schematic analysis products, including, Siemens says, how deeper Xpedition integration surfaces DC drop pass and fail status inside the layout tool.

What you will learn:

• Using the new generic 100G PAMn models and IBIS 7.2 features for 100G Ethernet and 112G OIF-CEI designs
• Updated compliance wizards and the latest OIF-CEI-05.2 standards, up to 224G
• New batch support for DDR5 CUDIMMs, enabling simulation of DDR5 modules above 6400 MT/s
• Tracking real-time DC drop pass and fail status directly within Xpedition Layout via the new EDM to HyperLynx integration
• Improvements in the Touchstone viewer and time-domain response for faster diagnostic analysis, and the full release of the PDN Time Domain analysis wizard
• Unified ground plane modeling, automated S-parameter extraction flows and enhanced 3D parametric modeling
• Parallel DSE processing, reducing the time complex design sweeps take
• Accelerating design sign-off with HyperLynx DRC, and HyperLynx Schematic Analysis for faster access to component intelligence

Who should attend

• PCB layout designers
• Signal integrity and power integrity specialists
• Hardware engineers
• Engineering managers

Tools covered

HyperLynx Signal Integrity, HyperLynx Power Integrity, HyperLynx Advanced Solvers, HyperLynx Schematic Analysis, HyperLynx AMS, HyperLynx DRC, HyperLynx DSE

Speakers

Session time

Registration and attendance is completely free. Time sourced from the official ON24 multi-session registration page.

Why GSAS is sharing this

GSAS is an authorized engineering partner for Siemens EDA (formerly Mentor Graphics) in India, covering the Xpedition, HyperLynx and PADS Pro portfolio. Indian PCB design and layout teams get this guidance directly from the Siemens EDA product and technical marketing team that owns these releases.

If your team is running DDR5 above 6400 MT/s or moving to 112G and 224G SerDes channels, talk to us.

This session is part of Siemens EDA’s EBS Expert Series. The July and August 2026 lineup covers the earlier sessions in the same series.

Register free on ON24 →