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Siemens EDA: Best Practices for TDR Simulations in HyperLynx

Siemens EDA: Best Practices for TDR Simulations in HyperLynx, register to attend Save Your Seat →
Free registration
Date
Tuesday, 17 November 2026
Format
Online, free live webinar, 10:30 PM IST
Speakers
Venkata Akunuru (Application Engineer, Siemens EDA) and Weston Beal (Senior Application Engineer, Siemens EDA)
Cost
Free

Registration for Siemens EDA: Best Practices for TDR Simulations in HyperLynx is free and open online. Select Save Your Seat, or click the event image, to sign up.

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Webinar banner, Effective setup and best practices for TDR simulations

What’s covered

“Effective setup and best practices for TDR simulations” is a free Siemens EDA webinar on Tuesday, November 17, 2026 at 10:30 PM IST, presented by Venkata Akunuru and Weston Beal.

Siemens says the session explains why real-world TDR traces drift from textbook impedance, and how trace losses, DC resistance and vias reshape the waveform response. It breaks down how rise-time settings and limited S-parameter bandwidth trigger aliasing and ringing, and gives practical setup rules for interpreting TDR results with confidence.

What you will learn:

  • TDR setup in the HyperLynx Touchstone Viewer
  • S-parameter extraction

Who should attend

  • Signal integrity engineers
  • HyperLynx LineSim and BoardSim users
  • HyperLynx Advanced Solvers users

Tools covered

HyperLynx LineSim, HyperLynx BoardSim

Speakers

Venkata Akunuru

Application Engineer · Siemens EDA

Weston Beal

Senior Application Engineer · Siemens EDA

Venkata Akunuru focuses on the HyperLynx signal and power integrity toolset. He started as a signal integrity engineer at a PCB design and manufacturing company and joined Siemens in 2022. Weston Beal delivers advanced HyperLynx solutions to customers, runs signal and power integrity consulting engagements, and specializes in automating HyperLynx flows and writing custom HyperLynx DRC rules. His Siemens bio notes earlier signal integrity roles at Sun Microsystems, Compaq and Micron Technology.

Session time

RegionTime
IndiaTuesday, November 17, 2026, 10:30 PM IST
US Pacific9:00 AM PST

Registration is free, and the session runs one hour. Time, speakers and abstract sourced from the official ON24 multi-session registration page.

Why GSAS is sharing this

GSAS is an authorized engineering partner for Siemens EDA (formerly Mentor Graphics) in India, covering the Xpedition, HyperLynx and Valor portfolio. Understanding why TDR results differ from the expected impedance is the core of this session, and it comes from Siemens application engineers who work on exactly that.

If your team is setting up HyperLynx signal integrity flows, talk to us.

This session is part of Siemens EDA’s EBS Expert Series, which also runs What’s New in Valor NPI 2610 on 11 November and Improve signal integrity using Backdrill on 19 November.

Register free on ON24 →

Frequently asked questions

What time is the TDR best practices webinar in India?
10:30 PM IST on Tuesday, 17 November 2026, which is 9:00 AM PST. The session runs one hour.
Who should attend?
Siemens aims it at signal integrity engineers and users of HyperLynx LineSim, BoardSim and Advanced Solvers.
What does the session cover?
Why real-world TDR traces drift from textbook impedance because of trace losses, DC resistance and vias; how rise-time settings and limited S-parameter bandwidth cause aliasing and ringing; TDR setup in the HyperLynx Touchstone Viewer; and S-parameter extraction.
Is the webinar free?
Yes. Registration is open on Siemens EDA's ON24 page, which lists no fee.
Who runs this webinar, Siemens or GSAS?
Siemens EDA runs it as part of its EBS Expert Series. GSAS Micro Systems is an authorized engineering partner for Siemens EDA in India and shares the session with Indian signal integrity teams.