Siemens EDA and Intel Foundry: The Bridge to Scale for AI and HPC

What’s covered

The “bridge” to scale for AI and HPC applications is a free Siemens EDA webinar on Wednesday, October 28, 2026 at 8:30 PM IST, presented with Intel Foundry, covering how substrate-embedded silicon bridges enable cost-effective heterogeneous integration, Intel Foundry’s EMIB and EMIB-T offerings, and a Siemens reference design and verification workflow.

Monolithic scaling has stopped being the cheapest way to add compute. AI and HPC parts are now assemblies: multiple chiplets, often from different processes and different fabs, connected at densities a conventional package substrate cannot reach. A substrate-embedded silicon bridge is the connector for that problem, a small piece of silicon buried in the substrate carrying high-density routing only where two dies need to talk.

This session is a joint Siemens EDA and Intel Foundry presentation covering both halves: the technology and the flow that designs it.

What is covered:

• The demand drivers pushing advanced IC design toward heterogeneous integration
• How substrate-embedded silicon bridges work, and where they fit against other advanced packaging approaches
• Intel Foundry’s EMIB and EMIB-T offerings
• A Siemens reference workflow for the integrated design and verification problem: inter-chiplet connectivity, thermal management and power integrity

Who should attend

• Package designers and 3D IC engineers working on multi-die assemblies
• IC design and verification engineers whose parts are heading toward chiplet architectures
• System architects evaluating heterogeneous integration for AI or HPC designs

Why the packaging flow is the hard part

The physics of an embedded bridge is well understood. The engineering difficulty is that a multi-die assembly stops being separable into “the chip problem” and “the package problem”. Inter-chiplet connectivity, thermal behaviour and power delivery are coupled across the whole assembly, so they have to be designed and verified against one connected model rather than handed between teams as deliverables.

That is the gap the design flow has to close, and it is why a packaging session like this one spends as much time on workflow as on process technology.

Speakers

Session time

Time, speakers and abstract sourced from the official Siemens registration page.

Why GSAS is sharing this

GSAS Micro Systems is an authorized Siemens EDA engineering partner in India (formerly Mentor Graphics), across the IC and board portfolios. Indian teams moving from single-die parts to multi-die assemblies face the packaging and verification problem this session describes, usually before they have a flow for it.

The Siemens tools in that flow that we supply include Innovator3D IC for multi-die layout and Xpedition Package Designer for package design.

If your roadmap includes chiplets or advanced packaging, talk to us.

Register on the Siemens webinar page →