NI Ettus USRP E320
Software Defined Radio2x2 MIMO software defined radio with embedded Arm processor, Zynq SoC FPGA, 70 MHz to 6 GHz coverage, and standalone networked operation. Buy in India from GSAS Micro Systems.
Frequency
70 MHz – 6 GHz (RX), 47 MHz – 6 GHz (TX)
Channels
2 Tx / 2 Rx (full duplex MIMO)
Bandwidth
Up to 56 MHz per channel
Processing
Zynq SoC (Arm Cortex-A9 + FPGA)
Interface
SFP+ (1/10 GbE, Aurora), RJ45 1 GbE
Operation
Standalone networked or host-driven
Overview
About NI Ettus USRP E320
The NI Ettus USRP E320 is a 2x2 MIMO software defined radio platform with embedded processing, covering 70 MHz to 6 GHz on receive and 47 MHz to 6 GHz on transmit, with up to 56 MHz of instantaneous bandwidth per channel. Built around a Xilinx Zynq-7045 SoC (dual Arm Cortex-A9 + FPGA fabric) and the Analog Devices AD9361 RF IC, the E320 runs a full Linux environment onboard, enabling standalone, networked SDR operation without a host computer.
USRP E320 Specifications
| Feature | Specification |
|---|---|
| Frequency Range | 70 MHz – 6 GHz (RX), 47 MHz – 6 GHz (TX) |
| Channels | 2 Tx / 2 Rx (full duplex MIMO) |
| Instantaneous Bandwidth | Up to 56 MHz per channel |
| RF IC | Analog Devices AD9361 |
| Processing | Xilinx Zynq-7045 SoC |
| CPU | Dual Arm Cortex-A9 |
| FPGA | Zynq-7045 programmable logic |
| Memory | 1 GB DDR3 |
| Interface | SFP+ (1 GbE, 10 GbE or Aurora), RJ45 1 GbE, USB host, micro-USB console |
| GPSDO | Internal GPS Disciplined Oscillator |
| Storage | SD card (Linux root filesystem) |
| Power | 6–15 VDC (20 W typical) |
| Software | UHD, GNU Radio, OpenAirInterface |
Embedded Standalone Operation
The E320’s dual Arm Cortex-A9 processors run an OpenEmbedded-based Linux environment, enabling the SDR to operate as a standalone networked appliance. Engineers deploy UHD applications, GNU Radio flowgraphs, or custom C++/Python signal processing directly on the device, no host laptop required. Gigabit Ethernet provides remote access and high-throughput streaming for distributed deployment scenarios including spectrum monitoring arrays, cellular base station emulators, and autonomous wireless testbeds.
Built-in GPSDO
The internal GPS Disciplined Oscillator provides GPS-locked 10 MHz reference and PPS timing signals, enabling frequency accuracy to parts-per-billion levels and GPS-timestamped captures. This is essential for deployed spectrum monitoring, direction finding, geolocation applications, and any multi-node system requiring time-synchronized measurements across distributed E320 units.
Applications
The USRP E320 serves as a standalone wireless research platform for 5G NR prototyping, LTE network simulation (via OpenAirInterface), cognitive radio experiments, spectrum monitoring, radar prototyping, and field-deployed RF sensing. The 2x2 MIMO capability enables beamforming, spatial multiplexing, and diversity reception research in a self-contained, network-accessible form factor.
GSAS Micro Systems provides the USRP E320 alongside the full NI Ettus USRP portfolio available through Digilent, with guidance on USRP model selection, antenna configuration, and UHD/GNU Radio deployment for academic and R&D teams across Bengaluru, Chennai, Hyderabad, Delhi NCR, Mumbai, and Pune.
Blog
Digilent Insights
Real-World SDR Applications: 5G Research, Satellites, IoT and ADS-B
Where software defined radio actually earns its place: 5G and 6G waveform research, spectrum monitoring, weather satellite reception, GNSS work, LoRaWAN debugging, aircraft tracking over 1090 MHz, and reconfigurable instrument prototyping. A practical map from GSAS Micro Systems, an authorized Digilent engineering partner in India, with a framework for matching a USRP platform to the job.
What Is Software Defined Radio (SDR)? A Practical Explainer for Indian Engineering Teams
Software defined radio moves the work of filtering, modulation and demodulation out of fixed hardware and into software running on processors and FPGAs. This explainer from GSAS Micro Systems covers what SDR is, how it differs from a traditional radio, what the signal chain looks like, why the FPGA matters, and how to pick a USRP radio in India.
ZedBoard FPGA-in-the-Loop: HDL Verifier vs HDL Coder
Teams asking for FPGA-in-the-Loop on a ZedBoard usually name HDL Coder and SoC Blockset. FIL is actually HDL Verifier. Here is the correct product split, the JTAG versus Ethernet decision, and the 2015-era advice that is still sending Indian teams down the wrong path.
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