Via Plating Reliability: Why Thin Barrels Fail and How Simulation Prevents It

A plated-through hole (PTH) that passes electrical test at the factory can still fail in the field. The failure mode is well known to PCB reliability engineers: the via barrel, the copper cylinder lining the drilled hole, is thinner at the midpoint than at the top and bottom. During thermal cycling (power-on/power-off, environmental temperature changes), the barrel expands and contracts in the Z-axis.

If the midpoint copper is too thin, the barrel cracks under repeated thermal strain. The via develops an intermittent open, a failure that passes continuity testing at room temperature but opens at elevated temperature when thermal expansion stresses the weakest point.

This is not a manufacturing defect in the traditional sense. The plating process worked as the physics dictated, current density is always lower at the midpoint of a deep hole than at its mouth, and the copper thickness follows accordingly. The defect is a predictable consequence of the electrochemistry that Elsyca PCBPlate can simulate and quantify before the board is fabricated.

The Electrochemistry of Via Plating

When a PCB panel enters the plating bath, current flows from the anodes through the electrolyte to the copper surfaces. For surface features, pads, traces, planes, the current path is straightforward and the copper deposition is relatively uniform (subject to the panel-level distribution effects that PCBBalance addresses).

For a plated-through hole, the situation is fundamentally different. Current must flow down the electrolyte column inside the hole to reach the barrel midpoint. This column presents an additional electrolyte resistance, the deeper the hole (higher aspect ratio), the greater the resistance, and the less current reaches the midpoint.

The result is a characteristic thickness profile: thick copper at the hole mouth (where current access is easy), progressively thinner copper towards the midpoint (where the electrolyte resistance limits current), and thick copper again at the opposite mouth. For standard aspect ratios (depth-to-diameter ratio of 6:1 to 8:1), the midpoint thickness can be 40-60% of the mouth thickness. For high-aspect-ratio vias (10:1 and above), the ratio is worse.

IPC-6012 Class 3 (high-reliability electronics) requires a minimum of 25 micrometres of copper in the via barrel. If the mouth has 35 micrometres and the midpoint has only 15 micrometres, the board fails the reliability requirement, even though the average copper thickness is nominally within specification.

What PCBPlate Predicts

PCBPlate’s tertiary current distribution model captures the mass transport and electrolyte resistance effects inside via holes. The simulation predicts:

• Copper thickness at the barrel midpoint: the critical reliability metric
• Thickness distribution along the barrel length: the full profile from mouth to mouth
• Effect of via diameter and aspect ratio: how design choices influence plating outcome
• Effect of process parameters: how current density, pulse waveform, and additive chemistry affect via plating

For designs with blind vias and microvias (HDI designs), the simulation also predicts copper fill quality, whether the via fills completely or leaves a void that compromises reliability.

Practical Implications for Indian PCB Manufacturing

India’s PCB manufacturing sector is investing in higher-layer-count, higher-aspect-ratio production capability. As Indian fabricators in Bengaluru, Pune, Chennai, and other centres take on 10+ layer designs with aspect ratios exceeding 8:1, via plating uniformity becomes a yield-limiting parameter.

For Indian PCB designers, PCBPlate provides early visibility into via plating risks:

Design-stage via sizing. Before finalising the drill table, simulate the plating outcome for proposed via diameters and aspect ratios. If the simulation predicts thin barrels, increase the via diameter or reduce the aspect ratio before releasing the design.

Fabricator selection. Different fabricators have different plating capabilities (cell geometry, chemistry, pulse plating). PCBPlate can model the specific plating environment of a target fabricator to predict whether a given design will meet thickness requirements on that fabricator’s line.

Reliability qualification. For high-reliability applications (defence, aerospace, medical, automotive), PCBPlate provides quantitative evidence that the via plating will meet IPC-6012 Class 3 requirements, supporting the reliability qualification dossier.

Pairing with PCBBalance

PCBBalance addresses the surface copper density imbalance that affects panel-level current distribution. PCBPlate addresses the via-level current distribution within individual holes. Together, they provide complete plating prediction, from the macro (panel) level to the micro (via barrel) level.

The recommended workflow:

1. Run PCBBalance to optimise copper balance across all layers
2. Run PCBPlate to verify via plating thickness for the balanced design
3. Adjust via sizing or process parameters if any vias fall below minimum thickness
4. Release design with confidence that plating will meet specification

Why Buy from GSAS

GSAS provides the complete Elsyca PCB simulation suite, PCBPlate and PCBBalance, in India. Our team supports PCB design and manufacturing operations in Bengaluru, Hyderabad, Chennai, Pune, Mumbai, Delhi NCR, and Visakhapatnam with licensing, training, and application support.

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