Siemens EDA: Chiplet-to-Chiplet Design with UCIe

What’s covered

“Chiplet-to-Chiplet design with UCIe” is a free Siemens EDA live webinar on Wednesday, December 2, 2026 at 9:30 PM IST, presented by Keith Felton, Ahmed ElKhamisi and Bryan McDevitt.

Siemens notes that the semiconductor industry is moving from monolithic SoC design to chiplet-based systems, while AI compute workloads demand higher throughput from die-to-die (D2D) connectivity. Siemens says UCIe (Universal Chiplet Interconnect Express) delivers the performance, power and area advantages those workloads need, but that reaching the required performance brings signal integrity challenges, from crosstalk and reflections to process variation.

The session explores emerging D2D connectivity applications and the bandwidth demands that make UCIe signaling a necessity.

What you will learn:

• How to quickly construct and capture die-to-die UCIe interfaces through rapid package assembly pathfinding
• How to optimize system performance, power and area (PPA)
• How shift-left early-analysis methodologies reduce design risk for advanced architectures
• How simulation-to-silicon correlation ensures that design intent translates into reliable hardware

Who should attend

• IC and IC package verification managers and directors
• IC and IC package design managers
• 3D IC program leads
• CAD and methodology managers
• IC and chiplet designers
• Semiconductor package and substrate designers
• System and micro architects
• Verification engineers working in physical verification and SI/PI

Tools covered

Innovator3D IC Integrator, Innovator3D IC Layout, Innovator3D IC Protocol Analyzer

Speakers

Keith Felton has worked in IC package design since the late 1980s and drives the strategy for Siemens’ multi-substrate prototyping, design and verification solution for high-density advanced packages. Ahmed ElKhamisi specializes in the Innovator3D IC Integrator tool and its integration with Calibre 3DSTACK. Bryan McDevitt has spent 18 years at Siemens EDA supporting board- and package-level simulation with HyperLynx, and presents the Innovator3D IC Protocol Analyzer part of the workflow.

Session time

Registration is free. Time, speakers and abstract sourced from the official Siemens webinar page.

Why GSAS is sharing this

GSAS is an authorized engineering partner for Siemens EDA (formerly Mentor Graphics) in India, including the Innovator3D IC Layout tool this session covers. Indian teams moving from monolithic SoCs to chiplets face the same die-to-die design and signal integrity questions this session addresses.

If your team is planning a chiplet or advanced package design, talk to us.

Keith Felton also presents Siemens’ bridge to scale for AI and HPC webinar with Intel Foundry on 28 October.

Register free on Siemens →