Arm Cortex Processor Family: The Complete List and…

If you have tried to draw the Arm Cortex processor family on a whiteboard, you have probably ended up with three branches, two dozen part numbers, and at least one engineer arguing about whether Cortex-X counts as Cortex-A. This guide is the single reference page for every Arm Cortex core, grouped by profile, with enough architectural context that a system engineer can build a short list. GSAS is Arm’s authorized partner in India for Arm Development Tools, and this page is maintained by the same team that supports Arm Development Studio, Keil MDK and the Arm Cortex tooling stack on Indian product benches.

The Arm Cortex processor family replaces the older ARM7, ARM9 and ARM11 classic cores. It is split into three profiles: Cortex-A for application-class silicon (smartphones, Linux SBCs, automotive infotainment), Cortex-R for hard real-time silicon (brake ECUs, storage controllers, 5G baseband), and Cortex-M for microcontroller-class silicon (BLE sensors, motor control, edge AI nodes). Every Cortex core, from the Cortex-M0+ on a Raspberry Pi RP2040 to the Cortex-X4 on a flagship phone SoC, sits in exactly one of those three buckets.

The Arm Cortex Processor Family: What the Three Profiles Actually Mean

The Arm Cortex processor family is organized by the Armv architecture profile letter each core implements: A-profile, R-profile or M-profile. These are not marketing buckets, they are different architecture specifications in the Arm Architecture Reference Manual, with different instruction sets, exception models and memory models.

Cortex-A, Application profile. A-profile cores implement Armv7-A, Armv8-A or Armv9-A. They run a rich OS (Linux, Android, QNX, Windows on Arm), have a memory management unit (MMU) with full virtual memory, support SMP clustering with DynamIQ, and almost always ship with NEON/SVE SIMD and an FPU. If it boots U-Boot and runs a Yocto image, you are on Cortex-A.

Cortex-R, Real-Time profile. R-profile cores implement Armv7-R or Armv8-R. They replace the MMU with a memory protection unit (MPU), giving deterministic address translation, no TLB misses, no page walks, no jitter. Most Cortex-R cores run in dual-core lockstep, where two cores execute the same instruction stream in parallel and compare outputs to detect single-event upsets. That is why Cortex-R dominates ISO 26262 ASIL-D automotive safety islands, HDD/SSD controllers and 5G baseband modems.

Cortex-M, Microcontroller profile. M-profile cores implement Armv6-M, Armv7-M or Armv8-M. They use Thumb-only (M0/M0+/M1) or Thumb-2 (M3 and above) encoding to keep code density high and silicon area low. They boot directly from a vector table in flash, support deterministic interrupt latency through the Nested Vectored Interrupt Controller (NVIC), and are the basis of every modern Arm microcontroller, STM32, NXP LPC/Kinetis, TI Sitara/MSP, Renesas RA, Infineon PSoC, Microchip SAM, Nordic nRF, Alif Ensemble, Raspberry Pi RP2040 and RP2350.

The generation letter tells you how old the architecture is. Armv7 is the 32-bit era. Armv8 introduces 64-bit (AArch64) and, in A-profile, pointer authentication and memory tagging. Armv9 adds SVE2, confidential compute (CCA), and in M-profile, Helium vector extensions.

Cortex-A Complete List: Every Application Processor Arm Has Shipped

Cortex-A is the largest branch of the family, every Android phone, every Linux SBC, and most automotive infotainment and ADAS domain controllers. The complete list of Cortex-A cores, grouped by Armv generation:

Core	Armv Generation	Cluster Role	Typical Workload
Cortex-A5	Armv7-A	Single/LITTLE	Low-cost feature phones, early MPU SoCs
Cortex-A7	Armv7-A	LITTLE	Entry-level smartphones, low-power Linux
Cortex-A8	Armv7-A	Single	TI Sitara AM335x, BeagleBone Black era
Cortex-A9	Armv7-A	Single/SMP	Xilinx Zynq-7000, industrial Linux
Cortex-A12	Armv7-A	Mid	Mid-tier Android (short-lived)
Cortex-A15	Armv7-A	big	Early big.LITTLE, Exynos 5, Tegra K1
Cortex-A17	Armv7-A	Mid/big	Refreshed A12 for mid-tier Android
Cortex-A32	Armv8-A (32-bit only)	LITTLE	AArch32 industrial MCU-plus
Cortex-A34	Armv8-A (64-bit only)	LITTLE	Entry AArch64 for IoT gateways
Cortex-A35	Armv8-A	LITTLE	Entry 64-bit smartphones, smart TV
Cortex-A53	Armv8-A	LITTLE	Raspberry Pi 3, Amlogic S905, NXP i.MX8
Cortex-A55	Armv8.2-A	LITTLE	Raspberry Pi 5, NXP i.MX9, Rockchip RK3588
Cortex-A57	Armv8-A	big	Nvidia Tegra X1, Jetson Nano era
Cortex-A65	Armv8.2-A	LITTLE (SMT)	Infrastructure / automotive cockpit
Cortex-A72	Armv8-A	big	Raspberry Pi 4, NXP LS1046, Marvell Armada
Cortex-A73	Armv8-A	big	Kirin 960, Amlogic S922
Cortex-A75	Armv8.2-A	big	Snapdragon 845, Exynos 9810
Cortex-A76	Armv8.2-A	big	Kirin 980, Rockchip RK3588 big cluster
Cortex-A77	Armv8.2-A	big	Snapdragon 865
Cortex-A78	Armv8.2-A	big	Snapdragon 888, MediaTek Dimensity 1200
Cortex-A78AE	Armv8.2-A	big (automotive)	Nvidia Orin, Renesas R-Car V4H
Cortex-A510	Armv9-A	LITTLE	Snapdragon 8 Gen 1, Dimensity 9000
Cortex-A520	Armv9.2-A	LITTLE	Snapdragon 8 Gen 3, Dimensity 9300
Cortex-A710	Armv9-A	Mid/big	Snapdragon 8 Gen 1 middle cluster
Cortex-A715	Armv9-A	Mid/big	Snapdragon 8 Gen 2 middle cluster
Cortex-A720	Armv9.2-A	Mid/big	Snapdragon 8 Gen 3 middle cluster
Cortex-A725	Armv9.2-A	Mid/big	Next-gen Android flagship middle

Cortex-X / C1 premium cluster. Starting with Cortex-X1, Arm added a premium performance tier that sits alongside Cortex-A inside a DynamIQ cluster. X-series cores are not “Cortex-A X”, they are their own product line, optimized for single-thread peak rather than perf-per-watt. The sequence is X1 (Armv8.2-A, paired with A78/A55), X2 (Armv9-A, A710/A510), X3 (Armv9-A, A715/A510), X4 (Armv9.2-A, A720/A520), and Cortex-X925 (Armv9.2-A, codename Blackhawk, Arm’s 2024 X-flagship). In 2025 Arm reorganised the premium CPU brand under the C-series umbrella: C1-Nano / C1-Pro / C1-Premium / C1-Ultra, where C1-Ultra is the successor to X925. (Note: there is no “Cortex-X5”, Arm jumped the X-numbering directly from X4 to X925, then to C1-Ultra.) On an Indian Linux SBC bench you will almost never see a Cortex-X / C1-Ultra, they are largely exclusive to flagship smartphone and high-end automotive SoCs.

Neoverse (N1, V1, N2, V2, N3, V3) is Arm’s infrastructure/server family, sibling to Cortex-A but aimed at datacentre workloads and hyperscale inference. We cover it separately in our Arm Development Studio post on Cortex-A, Cortex-R and Neoverse workflows.

Cortex-R Complete List: Every Real-Time Processor

Cortex-R is the smallest branch by part-number count but the most important one for functional safety. Every Cortex-R core supports dual-core lockstep, which is the basis for ISO 26262 ASIL-B / ASIL-D certification in automotive silicon.

Core	Armv Generation	Lockstep	Target Workload
Cortex-R4	Armv7-R	Yes	Early brake and ABS ECUs, HDD controllers
Cortex-R5	Armv7-R	Yes (dual-core lockstep)	TI Hercules, Xilinx Zynq UltraScale+ RPU, storage controllers
Cortex-R7	Armv7-R	Yes	LTE/4G baseband, automotive domain
Cortex-R8	Armv7-R	Yes (quad-core capable)	5G baseband modems, enterprise SSD controllers
Cortex-R52	Armv8-R (32-bit)	Yes (hard lockstep, hypervisor)	NXP S32Z/S32E, automotive zonal ECUs, Cortex-R safety islands (Infineon AURIX uses TriCore, not Cortex-R)
Cortex-R52+	Armv8-R (32-bit)	Yes	Next-gen automotive domain controllers, vehicle motion ECUs
Cortex-R82	Armv8-R (64-bit)	Yes	Enterprise SSD/NVMe computational storage, first 64-bit real-time core

The R52 family is the one that matters for Indian automotive Tier-1s right now. It is the first Cortex-R to support an Armv8-R hypervisor, letting multiple safety partitions run on the same physical core without interference, which is why NXP S32Z/S32E and newer zonal ECU designs pick it for the ASIL-D safety island. The R82 is the first 64-bit Cortex-R, designed for computational storage where the SSD controller runs Linux on one set of cores and handles real-time flash management on another.

Cortex-M Complete List: Every Microcontroller-Class Processor

Cortex-M is the branch that touches the most silicon by volume. Nearly every Arm microcontroller on the market, and every one of the STM32, NXP, TI, Renesas, Infineon, Microchip and Nordic devices we see on Indian product benches, is built around a Cortex-M core. Here is the complete list.

Core	Armv Generation	ISA	FPU	DSP	Helium MVE	TrustZone	Typical Workload
Cortex-M0	Armv6-M	Thumb (subset)	No	No	No	No	32-bit replacement for 8-bit MCUs
Cortex-M0+	Armv6-M	Thumb (subset)	No	No	No	No	RP2040, low-power BLE, coin-cell sensors
Cortex-M1	Armv6-M	Thumb (subset)	No	No	No	No	FPGA soft-core (Xilinx Artix/Kintex, Intel/Altera)
Cortex-M3	Armv7-M	Thumb-2	No	No (basic SIMD instr.)	No	No	STM32F1/F2, LPC17xx, industrial control
Cortex-M4	Armv7E-M	Thumb-2	Optional (single-precision)	Yes	No	No	STM32F4, motor control, audio DSP
Cortex-M4F	Armv7E-M	Thumb-2	Yes (single-precision)	Yes	No	No	nRF52840, STM32F4 with FPU, Kinetis K2x
Cortex-M7	Armv7E-M	Thumb-2	Optional (single or double)	Yes	No	No	STM32H7, i.MX RT10xx, NXP LPC54/55
Cortex-M23	Armv8-M Baseline	Thumb	No	No	No	Yes	Secure low-power IoT (SAM L11)
Cortex-M33	Armv8-M Mainline	Thumb-2	Optional	Optional	No	Yes	STM32L5/U5, nRF53/54, RP2350, PSoC 6
Cortex-M35P	Armv8-M Mainline	Thumb-2	Optional	Optional	No	Yes (+ anti-tamper)	Secure elements, payment MCUs
Cortex-M52	Armv8.1-M	Thumb-2	Yes	Yes	Yes (single-beat Helium)	Yes	Entry-level Armv8.1-M with Helium (newer Cortex-M52-based MCUs)
Cortex-M55	Armv8.1-M	Thumb-2	Yes	Yes	Yes (Helium)	Yes	Alif Ensemble, Himax, edge-AI MCUs
Cortex-M85	Armv8.1-M	Thumb-2	Yes	Yes	Yes (Helium)	Yes	Renesas RA8, high-end audio/ML MCUs

FPU distinction. M0/M0+/M1/M23 and the base M3 have no FPU, floating-point is software-emulated, fine for control loops but painful for DSP. Cortex-M4 has an optional single-precision FPU (the version with FPU is M4F). Cortex-M7 has an optional single- or double-precision FPU and is the first Cortex-M with a proper cache and dual-issue pipeline. M33, M35P, M55 and M85 all ship with FPU and DSP extensions.

Helium / M-Profile Vector Extension (MVE). The Cortex-M SIMD engine. Only on M55 and M85. It is what makes an MCU-class part capable of running a small neural network or audio pipeline without a dedicated NPU. Our Arm Cortex-M4 architecture deep dive covers the pre-Helium DSP extension.

TrustZone for Armv8-M. Every Armv8-M core, M23, M33, M35P, M55, M85, supports a hardware-enforced split between Secure and Non-Secure worlds on the same core. This is the basis for PSA Level 2/3 certification and for secure-boot on most new IoT silicon.

M1 is special. It is delivered as RTL soft-core, not a hard macro. Customers synthesize it into FPGA fabric, typically Xilinx Artix-7 or Kintex-7, when they need a Cortex-M inside a larger FPGA design.

Arm Cortex Family Comparison Table: One View of Every Core

The table engineers are actually searching for when they type “arm cortex processor list” into Google is a single unified view. Here it is, condensed.

Profile	Core	Armv	Signature Feature	Where You See It
M	M0 / M0+ / M1	v6-M	Tiny, Thumb-only	STM32C0, RP2040, FPGA soft-core
M	M3	v7-M	First Thumb-2 Cortex-M	STM32F1, LPC17xx
M	M4 / M4F	v7E-M	DSP extension + optional FPU	STM32F4, nRF52840, Kinetis K2x
M	M7	v7E-M	Dual-issue + cache	STM32H7, i.MX RT1060
M	M23	v8-M Baseline	TrustZone, low-power	SAM L11
M	M33	v8-M Mainline	TrustZone + FPU/DSP	STM32U5, nRF5340, RP2350
M	M35P	v8-M Mainline	Anti-tamper secure element	Payment/secure MCUs
M	M52	v8.1-M	Entry-level Helium MVE (single-beat)	Newer Cortex-M52 MCUs
M	M55	v8.1-M	Helium MVE	Alif Ensemble E1/E3
M	M85	v8.1-M	Highest perf Cortex-M	Renesas RA8
R	R4 / R5 / R7 / R8	v7-R	Lockstep, MPU	Storage controllers, baseband
R	R52 / R52+	v8-R	Hypervisor, hard lockstep	Automotive ASIL-D
R	R82	v8-R (64-bit)	First 64-bit Cortex-R	Computational storage
A	A5 / A7 / A8 / A9 / A12 / A15 / A17	v7-A	32-bit Linux-class	Zynq-7000, BeagleBone, old Android
A	A32 / A34 / A35 / A53 / A57 / A72 / A73	v8-A	First 64-bit Cortex-A	Raspberry Pi 3/4, NXP i.MX8
A	A55 / A65 / A75 / A76 / A77 / A78	v8.2-A	Mainstream Armv8.2	Snapdragon 8xx, RK3588
A	A510 / A710 / A715 / X1 / X2 / X3	v9-A	SVE2, confidential compute	Flagship Android 2022-2024
A	A520 / A720 / A725 / X4 / X925 / C1-Ultra	v9.2-A	Latest Armv9.2 generation (X925 = 2024 flagship; C1-Ultra = 2025 successor)	Flagship Android 2024-2025

Difference Between Arm and Cortex: Cleared Up

One of the most searched questions on this topic is “difference between arm and cortex”, so let us state it plainly. Arm is the company (Arm Holdings, formerly Arm Ltd) and the name of the instruction set architecture (the Arm ISA, across Armv1 through Armv9). Cortex is the current generation of Arm’s own processor cores. Before Cortex, Arm shipped ARM7TDMI (Game Boy Advance, Nokia 3310), ARM9 (early smartphones, industrial MCUs) and ARM11 (first iPhone, original Raspberry Pi). When Arm introduced Armv7 in the mid-2000s, they renamed the product line from “ARMx” to “Cortex” and split it into the three profiles we have been discussing.

“Cortex” is not a separate company and not a separate architecture, it is the marketing name for Arm’s own reference cores from Armv6-M and Armv7 onward. Other companies can license the Arm ISA and build their own cores, Apple, Qualcomm Nuvia, Ampere, Nvidia Denver, Marvell ThunderX, and those are “Arm processors” but not “Cortex processors”. Cortex is Arm-designed; custom Arm ISA cores from third parties are not. Legacy ARM7/9/11 silicon still exists in fielded products, those are Arm processors, just not Cortex ones.

How to Pick the Right Cortex Processor: A Short Decision Tree

When a customer walks in with a block diagram asking “which Cortex”, we run this decision tree in the first ten minutes.

Start with the OS question. If your product needs Linux, Android, QNX or Windows on Arm, anything with an MMU and virtual memory, you are on Cortex-A. Within Cortex-A:

Entry Linux SBC, cost-sensitive industrial: Cortex-A35, A53 or A55. Think Raspberry Pi 3/4/5, NXP i.MX 8M Mini/Plus, Rockchip RK3566.
Mainstream Linux / Android mid-tier: Cortex-A72, A76, A78. Think Raspberry Pi 4’s A72, RK3588’s A76 big cluster, automotive cockpit domain controllers.
Automotive safety-aware application class: Cortex-A78AE or the older A65AE. The “AE” stands for “Automotive Enhanced” and adds split-lock support so the same core can run in lockstep when a safety-critical workload demands it.
Flagship smartphone or high-end ADAS: Cortex-A720 / A725 + Cortex-X4 / X925 (or the 2025 successor C1-Ultra) in a DynamIQ cluster. This is the Snapdragon / Dimensity / Nvidia Orin territory.

If the workload is hard real-time with no OS or an RTOS that cannot tolerate jitter: brake ECUs, steering, storage controllers, 5G baseband, you are on Cortex-R. Within Cortex-R:

Legacy 32-bit real-time with MPU: Cortex-R4/R5 on TI Hercules, Xilinx Zynq UltraScale+ RPU.
Modern automotive ASIL-D with hypervisor: Cortex-R52 / R52+ on NXP S32Z/S32E, Infineon zonal ECUs.
64-bit computational storage or high-bandwidth real-time: Cortex-R82.

If you are building an MCU-class product: BLE sensor, motor drive, smart lock, wearable, small edge-AI node, you are on Cortex-M. Within Cortex-M:

Absolute lowest power / lowest cost: Cortex-M0+ (STM32C0, RP2040, nRF52810).
Classic industrial control / motor / audio: Cortex-M4F (nRF52840, STM32F4) or Cortex-M7 (STM32H7, i.MX RT1060).
Secure IoT with TrustZone: Cortex-M33 (STM32U5, nRF5340/nRF54, RP2350).
Edge AI and small ML inference on MCU: Cortex-M55 or M85 with Helium (Alif Ensemble, Renesas RA8, Himax WE2).

Silicon Vendors and Indian Availability: Who Ships Which Cortex Core

On an Indian embedded bench, the Cortex cores you actually see are the ones that ship in silicon from the vendors who dominate our distribution channel. The practical map:

STMicroelectronics: STM32C0 (M0+), STM32F0 (M0), STM32F1/F2 (M3), STM32F4/F7/L4 (M4/M4F), STM32H7 (M7 + M4), STM32U5/L5 (M33), STM32MP1/MP2 (Cortex-A7/A35/A53 + M4/M33 companion).
NXP: LPC (M0/M3/M4/M33), Kinetis K (M4F), i.MX RT crossover (M7 on RT10xx, M33 on RT11xx), i.MX 8/9 (A53/A55/A72/A75 + M7/M33 companion), S32 automotive (R52/R52+ lockstep, A53 Linux).
Texas Instruments: Sitara AM335x (A8), AM57xx/AM65xx (A15/A53 + R5F lockstep), TMS570 Hercules (R4/R5 lockstep).
Renesas: RA (M4/M23/M33/M85), RZ (A9/A53/A55), R-Car V3/V4 (A57/A76 for ADAS).
Infineon: PSoC 6 (M4F + M0+), TRAVEO T2G automotive (M4F / M7 / R52+).
Microchip: SAM D/L/E (M0+/M4F), SAM L11 (M23), PIC32CM (M0+/M23).
Nordic Semiconductor: nRF52810/32/40 (M4F), nRF5340 (dual M33, app + network), nRF54L/H (M33).
Alif Semiconductor: Ensemble E1/E3/E5/E7 (M55 + M55 + A32, edge AI).
Raspberry Pi: RP2040 is dual Cortex-M0+; RP2350 is dual Cortex-M33 (with optional Hazard3 RISC-V cores for the Pico 2); Raspberry Pi 5 uses BCM2712 with quad Cortex-A76; Pi 4 uses quad Cortex-A72; Pi 3 uses quad Cortex-A53.

All of these vendors are represented in the Indian distribution channel. The good news is that the Arm tooling stack, Keil MDK for Cortex-M, Arm Development Studio for Cortex-A/R/Neoverse, DSTREAM/ULINKpro for JTAG/SWD hardware debug, covers every core in this guide from a single vendor.