HyperLynx 2604: Every New Feature for India's Signal & Power Integrity Teams

Siemens has shipped HyperLynx 2604, and unlike a typical point release this one moves the needle in places that India’s signal-integrity and power-integrity teams genuinely feel: DDR5/LPDDR batch runs that now scale across cores, PCIe Gen 7 PAM4 at 128 GT/s, a brand-new beta wizard for time-domain PDN transients, GDSII reassignment that finally makes Calibre-to-HyperLynx hand-offs sane, and a Product Support Copilot wired into every tool in the family.

We sat through the nine official feature videos so you do not have to. What follows is a feature-by-feature walkthrough that combines the published release notes with what the demo videos actually show on screen, including the dialog paths, the parameters being toggled, and the workflow steps Siemens engineers glossed over in the blog summary.

If you support a hardware programme in Bengaluru, Pune, Hyderabad, Chennai, Mumbai or Delhi NCR, this is the release to plan a 2026 upgrade around.

Schematic Analysis: model creation that stops eating your week

Model creation has historically been the most painful part of SI workflows, passing CSVs in and out of Excel, hand-writing pin tables, and crashing out of Verify Models without being able to save your edits. HyperLynx 2604 rewrites this part of the tool almost end to end.

In Project Creator, launched from the Models tab in Xpedition Designer, the Save options now live inside the Verify Models dialog itself, and you can pick the target model library from a dropdown. Any edits you make inside Verify Models are preserved when you exit, open it again and the work is still there. (One caveat from the demo: changes made on the Models tab after the fact will likely invalidate those saved edits, so finish your Verify Models pass before you go back upstream.)

The biggest behavioural change is the scope of automatic model generation. Where prior releases would only seed models for passive two-pin parts and connectors, 2604 lets you initiate model creation for any part in the schematic, including active devices. The tool pulls part number, description, pin numbers, pin names and pin types straight from the Designer symbol and writes a partial model into the project library. You finish the model inside Schematic Analysis instead of starting from a blank template.

Unmodeled parts get three new resolution paths:

• Create and Assign from the BOM tab: works best for passives. Type description, value, tolerance, voltage and class for a capacitor, hit Create, and the model is generated without trawling through the modelling docs.
• Create Model from the model library: start from scratch or pull data from an existing Designer symbol.
• Import FPGA model from FPGA I/O Optimizer: the older Xchange/CSV export step is gone; I/O Optimizer’s native FCD file imports directly.

The Model Editor itself has been overhauled so it can finally replace Excel. Conditional formatting carries through, red cells flag missing data, green cells are verified. Fill-down on pin numbers follows the existing pattern and ignores prefixes like I/O/X. Pin names propagate the same way. Insert-row behaviour respects the count of rows you have highlighted, copy/paste from other models or spreadsheets behaves the way you would expect, and you can verify model requirements with a single click, no round-trip through Import.

There is also long-overdue support for bit swizzling and diff-pair polarity swapping at the model template level. For swizzled buses, enter |S in the Pin Mate section for bus or data pins and a number to denote lane size, this stops Schematic Analysis from raising false significance errors when a byte lane is intentionally re-ordered to ease routing. For polarity-swapped diff pairs, enter P in the Series column for both complementary pins and the false differential-input errors go away.

Analog-Mixed Signal: FMI grows up, DSE goes parallel

HyperLynx AMS 2510 introduced FMI (Functional Mock-up Interface) so AMS could swap models with other simulators via Functional Mock-up Units (FMUs). 2604 extends that to Boolean and integer signal ports, which is what the standard always intended and what makes FMU exchange genuinely useful for mixed-signal control logic.

The demo walks two scenarios. The first is a small design with two custom quantity-to-integer converters that sample a continuous input on each rising clock edge and emit the nearest integer. The FMU Export dialog now exposes integer signal ports alongside the usual quantity natures (voltage, current, angular velocity, etc.). The exported FMU is consumed by Siemens Twin Activate, which subtracts integer two from integer one, co-simulation runs, results visualised in both tools.

The second scenario is a more realistic three-level power inverter. A PartQuest Explore subsystem produces the digital gate signals, exports an FMU with Boolean signal ports, and HyperLynx AMS imports it via the FMU Import dialog. The Boolean ports are characterised in the import wizard, the FMU drops into the AMS model, and the co-simulation closes the loop on the inverter.

The second big AMS change is parallel processing in DSE optimisation studies. The HyperLynx AMS 2510 release first integrated Design Space Explorer. 2604 lets you run multiple design candidates concurrently. From the DSE integration dialog you can stay in the integrated wizard for a fast setup, or export the study and invoke the native DSE environment, and if you do that, you get an option to specify how many designs to execute simultaneously. On a workstation with the memory and cores to spare, this turns a multi-hour DSE sweep into something you can run over lunch.

HyperLynx DRC: Creepage Wizard, copilot, cleaner rules

The DRC team spent this release on quality and consolidation rather than new analysis. The Creepage Batch Wizard that arrived in the previous release is now launched directly from the HyperLynx DRC Application Launcher, no more digging through the install as a utility. The wizard performs multi-layer batch creepage checking against clearance rules defined in Xpedition Constraint Manager net classes, generates a violation report, and now reports the violation count in the wizard itself before you open the report (with a clear 0 if nothing was found).

Smaller usability touches that add up: the Distance column shows its unit of measurement inline; tooltips explain Layers-column inputs for targeting specific layers or layer groups in a batch run. Engineers running creepage in IEC 60664 / IEC 61010 contexts (medical, industrial power) will recognise how much friction this removes.

The bigger structural change is the scripting environment: HLDRC’s native scripting now supports action scripts, which closes out the transition from classic to modern capabilities and gives teams a foundation for the rule-based automation they used to keep in third-party scripts.

Several rule families were tightened. The decoupling-capacitor replacement rule has enhanced validation. The acute-angle rule has been refined to eliminate false violations. The net-length rule has a new violation visualisation in the board viewer. The component-alignment rule has upgraded accuracy. None of these are headline features, but anyone running DRC on real designs knows that “fewer false positives” is exactly the right place to invest.

Finally, the Product Support Copilot is now inside HyperLynx DRC. The demo shows two natural-language queries, “summarise all rules that perform electrical checks around vias” and a follow-up on the out-of-the-box EMI rule category, both answered against the live tool documentation without leaving DRC.

Power Integrity: DC Drop, Decoupling and the new Power Network view

PI 2604 is the densest section of the release. The Power Network interface has been reworked so power nets are displayed in groups consistent with the DC Drop Wizard view, expandable and collapsible individually. The Net Enable column is now sortable by clicking the header, and you can right-click to assign the rated voltage of one net to other subnets directly from the Power Supply Nets view. Double-clicking a row header zooms the board view to that net.

In the Power Network Topology view, VRM pins are collapsed by default and shown with the VRM name and total pin count, expand only when you need to drill into the underlying pins. ICs without assigned models are auto-collapsed to reduce visual clutter. DC drop results render directly inside the topology: voltage drop and power loss per IC (with a DC current sink assigned), colour-coded, red for failure against the constraint, green for pass, orange when results are stale and a new simulation is needed. VRM nodes report their output voltage and the total current for that rail.

On the Power Integrity Models dialog, two small but high-value additions:

• Include attached nets option on the IC tab, shows all reference designators connected to the currently selected power network setup, so you can manage assignments across a full power network without hunting.
• Pin and Net name filters on the Other Supply-Net Components tab, essential for finding specific pins on large ICs with hundreds of connections.

The interactive and batch DC Drop workflows pick up a setup-summary audit step that confirms required models are defined before you simulate. The summary shows simulated net, reference nets, VRM information, series passive devices, and per-IC sink current in a bar graph. Session-file save/reload arrives via Load and Save buttons. A new Keep Nets highlighted on exit option preserves net highlighting in the BoardSim workspace when you close the DC Drop dialog. And a single simulation can now generate HTML, XLS and CSV reports in one pass, with HTML extended to PDF export.

The DC Drop Shared Return Wizard inherits all those report-format options, and shared-return analysis performance is “significantly improved” when simulating multiple power supplies configured with multi-phase VRMs, a real win for modern server, automotive and AI-accelerator PDNs.

The new DC Metrics Viewer is the visual headline. Integrated into the post-layout environment, it opens automatically in a new tab after simulation (or manually via Power Integrity → Add DC Metrics View in the command bar). It displays voltage, drop, current, power density and via current across the power structure, with toggleable visibility for board outline, pins, vias and pin-name labels. Hovering the cursor surfaces dynamic detail for that location. Pass/fail thresholds are adjustable.

Over in HyperLynx Advanced Solvers, the DC Drop app gains a Pin Group assignment option for DC sink models. The DC Sink Type parameter now has three modes, Per Pin, Whole Array and the new Pin Group, and with Pin Group selected, the sink current value is applied to the entire group, treating IC pins as equal potential while distributing current based on the resistance matrix of the structure. That is a far more accurate representation of current distribution than the older per-pin or whole-array methods, particularly for modern BGAs with dozens of redundant power pins.

The Decoupling Wizard report in BoardSim has two new sections: a setup summary table for traceability and review, and transfer impedance plots versus frequency with per-port labelling so you can evaluate PDN performance against target impedance straight from the report.

Time-Domain Analysis Wizard: the beta PDN feature worth asking for

The most interesting PI addition is technically still beta and is enabled via your Siemens representative: a Time-Domain Analysis Wizard that extends HyperLynx PI into the time domain for post-layout PDN transient analysis.

The workflow: apply current sources at the dies of a package model to simulate switching events. The simulation captures voltage droop at the BGA pins and shows how decoupling capacitors drive voltage recovery, exactly the question your SoC vendor asks when they hand you a transient-current profile and a max-droop spec. Stimulus can be defined inside a built-in dialog or imported from a SPICE model file, and if the model has already been extracted you can reuse it instead of re-solving from scratch every time.

Output covers an overview report and time-domain waveforms in multiple formats. Constraints, max voltage droop, max peak-to-peak voltage, are fully configurable so the wizard can mark the result pass or fail against your spec. If you are designing for any modern AI accelerator, automotive SoC or DDR5 PDN, this is the wizard you want piloted now.

Touchstone Viewer, workspace ergonomics and Product Support Copilot

The general-purpose UI gets three updates worth knowing about.

The Touchstone Viewer finally adds port names directly to the legend, so a trace is identifiable at a glance instead of by index lookup. Graph customisation moves into a proper Edit Chart Style dialog: line type, line colour, plot-marker selection, axis labels and a plot title, everything you need so that exported graphs are annotated and ready to drop into a report without post-processing in another tool.

Sliding Panel Customisation lets you drag-and-drop groups to reorder them, and rearrange individual icons within a group. You are no longer stuck with Siemens’s default ordering, put the tools you use ten times an hour at your fingertips.

The Product Support Copilot is now available across HyperLynx SI/PI, Schematic Analysis, Advanced Solvers, DRC, and AMS: the entire HyperLynx family. It is part of the broader Siemens Fuse EDA AI System, and it runs as an in-app chat interface drawing from the tool’s documentation. Open it from the Assistance tab or type help in the search bar, then ask in plain language about a feature, a workflow, or a parameter. For new engineers, this is the difference between losing twenty minutes to documentation search and getting an answer in ten seconds.

SerDes: PCIe Gen 7 PAM4, multi-port crosstalk and CEI-224G

If you do high-speed serial work, this is the section to read carefully.

Multi-port models make crosstalk-aware compliance considerably less painful. Crosstalk settings have moved to the Transmitter/Receivers page so additional aggressors can be selected in one place. Endpoint TX assignments control whether aggressors are treated as NEXT or fixed, making the intent explicit instead of buried in side dialogs. PCIe reference package models now require explicit victim/NEXT/fixed-aggressor assignments, and the SerDes Compliance Batch Wizard analyses NEXT and fixed aggressor channels for coupling strength to the victim and auto-connects them to the PCIe reference package crosstalk channels, that keeps configuration spec-compliant by construction.

The Compliance Parameter Editor displays aggressor positions and reports list assignments for traceability. Simulation speed improves when reusing S-parameters for 4-port multi-port models such as chip-to-module configs. HTML reports now include multi-port graphics.

PCIe Gen 4 through Gen 6 configurations now support the spec-required coupled package models including NEXT and FEXT aggressors. Configs include upstream and downstream directions for correct RC and non-RC (NRC) model assignment. Protocol names are cleaner: Captive Channel replaces the older end-to-end naming. System board and add-in card naming stays consistent. The Analysis Options page now carries a usage-note section drawn from the config files, which is a real onboarding aid for engineers who do not live in the PCIe base spec.

PCIe Gen 7 is the headliner. Full support for PCI Express Base Spec 7.0 with PAM4 signalling at 128 GT/s. Configurations cover Captive Channel upstream and downstream, with full and reduced swing, and 29-tap equalisation. Each config ships with 32-port RC and NRC reference package S-parameters with one victim, four fixed and three NEXT aggressors for realistic high-speed crosstalk simulation. This is the kit you need to start Gen 7 channel work today.

OIF CEI-224G and IEEE 200G updates align the Compliance Wizard engine with COM 4.12. New metrics include signal-to-common-mode ratio for the channel, signal-quantisation noise, linear fit, pulse peak and ISI-updated SNR. Protocol coverage now spans CX, KR, C2C CDM variants for 200G, plus CEI-224G Long Reach, Medium Reach and the new Very Short Reach variants.

Smaller but useful protocol additions: Analog Devices’ GML2 at 3 and 6 Gbps across cable, PCB and system channels; channel metrics for SFF-8418 SFP-DD at Test Points TP2, TP3 and the Host Compliance Board; and a new option to toggle saving of supporting files in results directories, which can dramatically reduce results-directory size.

DDRx parallelisation: 2-10x faster batch runs out of the box

The single most-requested DDR feature in years lands in 2604: DDRx Batch Wizard parallelisation. The wizard now takes advantage of multiple cores on a single workstation to run simulations concurrently. Siemens’s own testing shows 2x to 10x performance gains, with the largest gains on complex designs, meaning anything with crosstalk and many aggressors, or anything using the Advanced IBIS-AMI flow.

The licensing model is unusually generous: a single DDRx licence already entitles you to two parallel simulations at no additional cost. If you need more parallelism, additional acceleration licences scale you up, but the baseline value uplift on existing licences is real.

Two other DDR additions are worth flagging.

Clock-forwarding support has been added to the Advanced IBIS-AMI flow. That means the actual data-strobe timing relative to the data bus is now incorporated for enhanced timing accuracy. It builds on the DDR Batch Wizard’s existing strength, supports both timed and wave-type clocked inputs, and works with the auto-levelling feature for automatic bus de-skew and more optimal timing results, simplifying timing closure on any DDR interface.

Sweeps in BoardSim post-layout. Previously, if you wanted to sweep buffer settings, terminations, stack-up parameters or power supplies, you had to export nets from post-layout into LineSim. 2604 lets you specify and run those sweeps directly in BoardSim. The workflow saving is significant.

The HTML report also now embeds the AMI settings used during simulation, so the AMI configuration is visible alongside the results, useful for documentation, peer review and post-mortems.

Advanced Solvers: pin thickness, GDSII reassignment

Two targeted additions to Advanced Solvers, both fixing real-world model-fidelity problems.

The Advanced Port Options dialog is expanded so you can alter ports and other external references on components without having to invoke Advanced Solvers separately. The new Pin Thickness parameter is the headline: it adds extra metal-pin thickness below the solder ball, bump or post, specifically for J-Lead connections. Defining this directly in BoardSim gives you a far more accurate physical representation in the EM solve, particularly for the connector and module families where the J-Lead contributes meaningfully to the parasitic profile.

The second addition tightens GDSII integration. GDSII is the lingua franca of fab handoff, but it carries no inherent EDA net or pin information, which has historically made GDSII-to-HyperLynx (via Calibre) a brittle hand-off. 2604 adds a Reassign From Properties dialog that lets you reassign nets, pins and materials by using the generic properties embedded in the GDSII file. Combined with 3-10x faster GDSII scanning and improved net/pin/material transfer, this turns a Calibre-driven flow from “doable but painful” into “routine.”

Why this matters for Indian engineering teams

The 2604 release lands cleanly on the four kinds of work that dominate India’s SI/PI bench right now:

• Automotive ECU and zonal-architecture programmes in Pune and the Chennai-Bengaluru corridor. Faster DDRx batch runs, the new Time-Domain PDN Wizard and the BoardSim sweep capabilities reduce the simulation gap between functional-safety review cycles. Schematic Analysis bit-swizzling and diff-pair polarity-swap support kill the false-positive noise that consumes review meetings.
• Semiconductor and SoC design houses in Bengaluru and Hyderabad. PCIe Gen 7 PAM4 at 128 GT/s with 32-port RC/NRC reference packages, multi-port crosstalk-aware compliance, and the OIF CEI-224G / IEEE 200G updates put SI verification on a footing for the next two silicon generations. GDSII reassignment closes the Calibre-to-HyperLynx loop that custom-silicon teams have lived with for years.
• 5G, mmWave and high-speed networking teams in Bengaluru, Hyderabad and Delhi NCR. The CEI-224G Very Short Reach, Long Reach and Medium Reach variants are exactly what 224G optical-module and switch programmes need. Touchstone Viewer port-name legends and Edit Chart Style mean you can hand over results that look like the published spec plots.
• Data-centre, AI-accelerator and industrial-PDN work in Chennai, Mumbai and Delhi NCR. The Time-Domain PDN Wizard, the DC Metrics Viewer, the Pin Group sink-model option in Advanced Solvers DC Drop, and the multi-phase VRM shared-return performance lift add up to a much more credible PDN sign-off story for high-current rails.

If your team is running an older HyperLynx (2510 or earlier), the upgrade case is unusually concrete: the DDRx parallelisation alone pays back the time spent on the upgrade within a single batch wizard run, and the Product Support Copilot meaningfully accelerates onboarding for the engineers you have hired into the bench in the last twelve months.

We have written previously about how Indian teams are using HyperLynx for signal and power integrity work, how it complements the Xpedition front-end as an add-on token, and the parallel reality that decoupling design from analysis brings. 2604 strengthens every one of those arguments.

FAQ

Does HyperLynx 2604 require new licences for the DDRx parallelisation?

No. A single DDRx licence already supports two parallel simulations at no additional cost. Beyond two, you scale with acceleration licences, useful for teams that want to push a full DDR5 channel sweep on a workstation with high core counts.

Is the Time-Domain Analysis Wizard included with HyperLynx PI 2604?

It is shipped as a beta feature. Customers need to contact their Siemens representative, or GSAS, as the authorised Siemens EDA engineering partner in India, to enable access in the 2604 build.

Is the Product Support Copilot available across all HyperLynx tools?

Yes. The Copilot is integrated across HyperLynx SI/PI, Schematic Analysis, Advanced Solvers, DRC and AMS in this release. It is part of the Siemens Fuse EDA AI System and runs as an in-app chat interface drawing on the tool’s documentation. Open it from the Assistance tab or type help in the search bar.

Will PCIe Gen 7 configurations work with reference packages from prior releases?

The Gen 7 configurations ship with their own 32-port RC and NRC reference package S-parameters (one victim, four fixed aggressors, three NEXT aggressors). Older Gen 4-6 channels also pick up updated coupled-package model support in this release, so a careful re-baseline is recommended when you move to 2604.

Does the GDSII reassignment require Calibre?

The reassignment dialog works from generic properties embedded in the GDSII file, so it does not strictly require a Calibre-generated GDSII, but the integration is specifically tightened for Calibre-to-HyperLynx flows, which is where most India custom-silicon teams will see the biggest workflow lift.

How does HyperLynx DRC’s Creepage Wizard differ from rules in Xpedition Constraint Manager?

The DRC Creepage Batch Wizard reads the clearance rules defined in Xpedition Constraint Manager net classes and runs a multi-layer creepage check from layout, producing a violation report. It is a layout-side verification of the rules you already capture upstream, the difference is that 2604 launches the wizard directly from the HyperLynx DRC Application Launcher, reports the violation count in the wizard itself before opening the report, and clarifies the Distance-column units and Layers-column inputs.

Where GSAS comes in

GSAS Micro Systems is the authorised Siemens EDA engineering partner in India, supporting customers across Bengaluru, Hyderabad, Chennai, Pune, Mumbai and Delhi NCR. We work alongside teams on HyperLynx pilots, Xpedition rollouts, methodology refresh, ECAD/MCAD bridges, and PDN/SI sign-off methodology. If you are evaluating HyperLynx for the first time, the most efficient path is to start with the Xpedition Standard trial, which includes a HyperLynx evaluation bench.

If you would like a walkthrough of any specific feature in this post, DDRx parallelisation, the Time-Domain PDN Wizard, GDSII reassignment, PCIe Gen 7, get in touch and we will schedule a working session with your bench.