Skip to main content
Setting many breakpoints in embedded flash memory during firmware debugging with a J-Link probe

Unlimited Flash Breakpoints Explained: How J-Link Does It and Which Models Include the License

GSAS Engineering · · 5 min read

Every embedded developer eventually hits the wall: you are chasing a bug through a driver, an RTOS task, and two interrupt handlers, and the debugger refuses the next breakpoint. The silicon is the limit. SEGGER puts the figures plainly: 2 hardware breakpoint units on ARM7/9 and 4 to 6 on Cortex-M, and that is all the chip has.

Unlimited Flash Breakpoints is SEGGER’s answer, and it is one of the most misunderstood features in the J-Link family, both in how it works and in which models actually include it. Both halves matter when you are choosing a probe.

The problem: breakpoints in flash are hard

A software breakpoint is simple in RAM: the debugger swaps an instruction for a breakpoint instruction and puts the original back later. Code executing in place from flash resists that trick, because flash is not byte-writable; changing one instruction means erasing and reprogramming a whole sector.

So debuggers normally fall back on the hardware comparators, all four-to-six of them. Complex debugging sessions, conditional-path hunting, and library-heavy codebases run out fast. And there is a second, less-known ceiling SEGGER documents: on most Cortex-M3 and Cortex-M4 devices, hardware breakpoints cannot be set in external memory at all, so firmware running from memory-mapped external flash can be undebugable with hardware units alone.

SEGGER’s technology takes the flash-reprogramming route and makes it practical. Per SEGGER’s documentation:

  • “The J-Link software reprograms a flash sector to set or clear a breakpoint.”
  • “Flash sectors are programmed only when necessary, typically when execution of the target program is started.” Setting ten breakpoints in the same sector costs one reprogram, not ten.
  • “A built-in instruction set simulator further reduces the number of required flash operations.” Where J-Link can simulate the instructions around a breakpoint, it avoids touching the flash at all.

The result, in SEGGER’s words, “minimizes delays for the user while maximizing the lifetime of the flash”, and “on microcontrollers with fast flash, the difference between breakpoints in RAM and in flash is hardly noticeable”. In day-to-day use, you set breakpoints in the IDE as if the limit did not exist; the probe handles the rest transparently.

It also reaches where hardware comparators cannot: SEGGER states the feature works “in both internal and external flash, including memory-mapped QSPI flash”, which is exactly the memory hardware breakpoints abandon on most Cortex-M3/M4 parts.

This is where teams get caught, and it is worth quoting SEGGER directly: “For all J-Trace and J-Link models higher than J-Link BASE, the Unlimited Flash Breakpoints feature is included”, and “J-Link BASE requires an upgrade BASE to PLUS.”

ProbeUnlimited Flash Breakpoints
J-Link BASE / BASE CompactNot included; requires the BASE-to-PLUS upgrade
J-Link PLUSIncluded (license preinstalled with J-Flash, Ozone, RDI)
J-Link ULTRAIncluded
J-Link PRO / PRO PoEIncluded
J-Link WiFiIncluded
J-Link EDU MiniIncluded, education-only license
J-Link OBStandard OB matches BASE; the OB PLUS option adds it

Two practical notes. First, the BASE-to-PLUS upgrade is a software license for a probe you already own, and it bundles more than breakpoints: J-Flash and J-Flash SPI, the Ozone debugger, monitor-mode debugging, and RDI come with it. Second, SEGGER offers a free 30-day trial license, requested by emailing your J-Link serial number to SEGGER, so a team on BASE probes can evaluate the workflow before buying the upgrade.

If you are still choosing a probe, the arithmetic is usually simple: the moment your debugging style wants more than a handful of breakpoints, the J-Link PLUS with everything preinstalled is the cleaner buy than BASE plus a later upgrade. Our J-Link buyer’s guide and PRO vs ULTRA comparison cover the rest of the decision.

Get flash breakpoints working in India

GSAS Micro Systems is an authorized SEGGER engineering partner in India. We supply every J-Link model and the BASE-to-PLUS upgrade with competitive pricing and short lead times, INR invoicing, and GST documentation, and our field application engineers in Bengaluru, Hyderabad, Chennai, Pune, Mumbai, and Delhi NCR help teams set up their debug workflows end to end.

Request a quote, or explore the full SEGGER portfolio at GSAS.

Interested in SEGGER tools?

Talk to our application engineers for personalized tool recommendations.

Frequently asked questions

How many hardware breakpoints does a Cortex-M microcontroller have?
Very few. SEGGER puts the figures at 2 on ARM7/9 and 4 to 6 on Cortex-M. Every breakpoint beyond that has to come from software techniques, which is what J-Link's Unlimited Flash Breakpoints provide for code running in flash.
How do J-Link Unlimited Flash Breakpoints work?
Per SEGGER, the J-Link software reprograms a flash sector to set or clear a breakpoint. Sectors are programmed only when necessary, typically when execution starts, and a built-in instruction set simulator further reduces the number of flash operations, which minimizes delays and maximizes flash lifetime.
Which J-Link models include Unlimited Flash Breakpoints?
SEGGER includes the feature with all J-Trace models and all J-Link models higher than the J-Link BASE, so PLUS, ULTRA, PRO, PRO PoE, and WiFi have it out of the box, and the EDU Mini includes it under its education-only license. The J-Link BASE and BASE Compact require SEGGER's BASE-to-PLUS upgrade.
Do flash breakpoints wear out my microcontroller's flash?
SEGGER designed the feature to minimize flash operations: sectors are reprogrammed only when necessary and an instruction set simulator avoids many programming cycles entirely, which SEGGER states maximizes the lifetime of the flash. On microcontrollers with fast flash, SEGGER notes the difference between RAM and flash breakpoints is hardly noticeable.
Do flash breakpoints work in external QSPI flash?
Yes. SEGGER states Unlimited Flash Breakpoints work in both internal and external flash, including memory-mapped QSPI flash. That matters because on most Cortex-M3 and Cortex-M4 devices, hardware breakpoints cannot be set in external memory at all.
How can I buy the BASE-to-PLUS upgrade or a J-Link with flash breakpoints in India?
GSAS Micro Systems, an authorized SEGGER engineering partner in India, supplies every J-Link model and the BASE-to-PLUS upgrade with competitive pricing and short lead times, INR invoicing, and local application engineering support.

Stay in the Loop

Get monthly compliance updates, product insights, and engineering best practices delivered to your inbox.

Related Articles

Embedded engineering workstation in India, illustrating the debug, analysis and design steps where AI now runs inside the process, supported by GSAS
Industry Insights

AI Inside the Engineering Process: What Is Worth Automating, and What Still Needs an Engineer

Arm, SEGGER, Perforce and Siemens EDA have each put AI inside a step of the engineering process rather than on top of it: debug, remediation, design entry, inference on the part. GSAS sets out the position behind our coverage of each: which steps are now worth automating, and which keep a human because the cost of being wrong is a recall.

21 Sept 2026 · 11 min read
Two test paths leaving the same device under test, one into a conformance suite that returns a passed report and one into a partner node that surfaces a field defect, showing why an ECU can clear a published suite and still fail in a vehicle, from GSAS Micro Systems India
Automotive Ethernet Automotive & Mobility

Automotive Ethernet Conformance: TC8 and Testing Above It

Summarising TC8 as a layer 1 to layer 4 suite is wrong in both directions. The public OPEN Alliance ECU test documents run from transmitter distortion up to a SOME/IP chapter with its own standardised test stub, and they contain exactly one time synchronisation test case. This is what those documents enumerate, chapter by chapter, what genuinely lives above their boundary, why a passing ECU can still fail against a partner node, and how much pre-compliance work a Tier-1 in India can honestly do in-house before a test house visit. Written by the GSAS Micro Systems engineering team in India.

29 Aug 2026 · 12 min read
Ladder chart of the T1 single-pair Ethernet family by data rate: 10BASE-T1S (802.3cg), 100BASE-T1 (802.3bw), 1000BASE-T1 (802.3bp), 2.5/5/10GBASE-T1 (802.3ch) and 25GBASE-T1 (802.3cy), one balanced pair across five IEEE standards, from GSAS Micro Systems India
Automotive Ethernet Automotive & Mobility

The T1 Family Explained: 10BASE-T1S to Multi-Gig 802.3ch

The T1 family is the set of single-pair Ethernet physical layers used in vehicles, and every member is documented separately inside a different datasheet. This guide puts all of them in one table with rate, symbol rate, line code, specified reach and cabling traced to public IEEE task force documents, then answers the two questions that keep coming back: why 100BASE-T1 has no auto-negotiation, and why one end has to be master. Written by the GSAS Micro Systems engineering team in India.

29 Aug 2026 · 13 min read