In short
Siemens EDA describes a PDN workflow, developed with AMD, for AMD Versal adaptive SoCs that starts from AMD Power Design Manager requirements and uses HyperLynx PI to model the VRM, planes and decoupling, check target impedance, and optimise capacitors with a genetic algorithm. On the AMD VCK190 evaluation board, Siemens reports decoupling capacitors cut from 172 to 111 and parts cost reduced by nearly 30%.
Adaptive SoCs such as AMD’s Versal family need clean power from DC up into the gigahertz range: stable rail voltages, controlled current transients, and low PDN impedance across that whole band. The traditional way to be safe is to add capacitors. Siemens notes that over-engineered PDNs carry excessive decoupling capacitors and add product cost and time to market.
An October 2025 Siemens EDA article describes a workflow, developed jointly by Siemens EDA and AMD, that replaces that caution with analysis. This post summarises it, including the results Siemens reports on a real AMD board. The article and its technical paper are linked under References.
The workflow
The flow starts with AMD Power Design Manager (PDM), which provides the initial power requirements and decoupling recommendations for the specific Versal device configuration. From there, HyperLynx PI:
- Models the complete power delivery system: the voltage regulator module (VRM), the PCB planes and the decoupling capacitors.
- Analyses PDN performance against the target impedance requirements.
- Optimises decoupling capacitor selection and placement with a genetic algorithm, which evolves the design over successive generations and improves the candidate variants each time.
The third step is the HyperLynx PDN Decoupling Optimizer. Rather than one engineer’s best guess, it produces a set of passing configurations that trade capacitor count, capacitor types, margin and parts cost against each other, so the team can choose.
Results on the AMD VCK190
Siemens applied the workflow to the AMD VCK190 evaluation board and reports:
| Metric | Before | After |
|---|---|---|
| Decoupling capacitors | 172 | 111 |
| Distinct capacitor part numbers | 7 | 6 |
| Parts cost | Baseline | Reduced by nearly 30% |
| Performance margin | Baseline | Slight improvement |
Fewer components also simplified the board layout. The figures are Siemens’ results for this one board; your savings depend on how conservative your starting design is.
Why it matters beyond the BOM
Siemens lists the business effects as lower BOM cost, simpler sourcing and inventory, better manufacturability from fewer placements, lower risk of design iterations, and more efficient use of board area.
The opposite failure matters too. Siemens notes that insufficient analysis can miss power integrity problems and force costly redesigns during prototyping or production. Analysis against a target impedance is what lets a team remove capacitors with confidence instead of hoping.
For Indian teams building Versal-based boards for defence electronics, communications, test and measurement or embedded vision, this is a repeatable method you can apply to each new board rather than a one-off tuning exercise. For the wider HyperLynx PDN feature set, see our HyperLynx SI/PI guide.
Working with GSAS
GSAS supports the Siemens EDA portfolio in India, including HyperLynx PI and the PDN Decoupling Optimizer, with local application engineers who can run the workflow with you on your own Versal or other high-current board. Talk to us from Bengaluru, Hyderabad, Chennai, Pune, Mumbai or Delhi NCR.
References
- Siemens EDA, Electronic Systems Design blog: Verification and optimization of power delivery networks for AMD Versal devices (7 October 2025)
- Siemens technical paper: Frequency-impedance verification of power delivery networks with HyperLynx PI for AMD Versal adaptive SoC devices
- AMD: Versal adaptive SoCs
- HyperLynx and the Siemens EDA partner page at GSAS
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