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Functional Safety

9 articles tagged with Functional Safety.

An ISO language standard open beside an embedded development board and debug probe, the toolchain qualification work GSAS Micro Systems supports in India
Compliance & Safety Solid Sands

Undefined Behaviour in Embedded C and C++

Undefined behaviour is not a bug your compiler owes you a warning about. ISO/IEC 9899 defines it as behaviour for which the standard 'imposes no requirements', and it signals it in three different ways with, in the standard's own words, 'no difference in emphasis' between them. Which is why code carrying undefined behaviour can pass every test on your bench and still change the day you upgrade the toolchain.

28 Jul 2026 · 16 min read
GSAS Micro Systems and Solid Sands partnership for compiler and library qualification in India
Functional Safety Solid Sands Automotive & Mobility

GSAS Partners with Solid Sands to Bring Compiler and Library Qualification to India

GSAS Micro Systems is now the India engineering partner for Solid Sands, makers of SuperTest and SuperGuard. The partnership brings compiler and standard-library qualification to Indian automotive, avionics, medical, and semiconductor teams, the toolchain-trust layer their safety standards require.

9 Jun 2026 · 5 min read
SEGGER J-Link debug probe connected to a motor-control development board on an Indian engineering bench, monitor mode debugging keeps PWM running while the foreground code is paused
Functional Safety SEGGER

SEGGER Monitor Mode Debugging: When Halting the CPU Breaks the Motor

Setting a breakpoint on a motor-control or DC-DC firmware target halts the PWM and lets the motor freewheel, or worse. SEGGER's Monitor Mode debugging keeps the time-critical interrupts running while the rest of the code halts. Here's how it works on Cortex-M, when to reach for it, and how Indian power-electronics teams use it.

23 May 2026 · 7 min read
Indian senior firmware engineer at a Pune medical-device firmware lab debugging a Cortex-M33 ASIL-B application running under Arm FuSa RTS, with MPU region configuration and event recorder output visible
Functional Safety Arm

Arm FuSa RTS in Production: MPU Isolation, Thread Watchdogs, and Safety Class API for Indian Medical and Industrial Firmware

Beyond the certification dossier: how Arm FuSa RTS actually works in production firmware. MPU-based spatial isolation, thread-watchdog patterns, and the Safety Class API that Indian medical-device, industrial-controls, and railway-signalling teams use to keep ASIL/SIL/Class-C designs running safely.

8 May 2026 · 13 min read
Indian functional-safety architect at a Hyderabad automotive ECU design centre evaluating STL, DCLS, Split-Lock, and Hybrid Mode fault-detection techniques with Cortex-R52 and Cortex-A AE datasheets visible
Functional Safety Arm Automotive & Mobility

STL vs DCLS vs Split-Lock vs Hybrid Mode: Picking the Right Fault-Detection Strategy for Indian Safety Programmes

Four different fault-detection techniques cover four different parts of the ASIL spectrum on Arm safety silicon, Software Test Library, Dual-Core Lock-Step, Split-Lock (Cortex-R52), and Hybrid Mode (Hunter-AE / Hayes-AE). The decision framework GSAS gives Indian Tier-1 / Tier-2 automotive teams, anchored on Arm's published functional-safety solutions.

8 May 2026 · 12 min read
Indian functional-safety engineer in a Pune automotive electronics centre reviewing Arm Compiler FuSa safety qualification documentation alongside compiler version control
Arm Compiler Arm Automotive & Mobility

Planning the AC6.16 LTS → AC6.22 LTS Migration for Indian FuSa Programs

Arm Compiler 6.16 LTS Term licenses are reaching end-of-life. AC6.22 LTS is the FuSa successor with new core support and the Certified C Library now bundled. This is the migration playbook GSAS gives Indian automotive, railway, and industrial teams in Bengaluru, Hyderabad, Chennai, and Pune.

7 May 2026 · 11 min read
Arm Cortex-R5 dual-lockstep processor block diagram on an Indian automotive Tier-1 functional safety bench with brake ECU under test
Cortex-R Arm

Arm Cortex-R Real-Time Processors: R5, R7, R52 for Indian Safety Critical

A deep-dive on the Arm Cortex-R family, R4, R5, R7, R8, R52, R52+, R82, for Indian automotive, industrial, and safety-critical teams. Lockstep, ISO 26262, silicon vendors, and the Cortex-R vs Cortex-M vs Cortex-A decision.

15 Apr 2026 · 12 min read
SEGGER J-Trace PRO connected to a Cortex-M ECU on an Indian automotive Tier-1 functional safety bench with Ozone trace timeline on screen
J-Trace SEGGER Automotive & Mobility

SEGGER J-Trace PRO: ISO 26262 and DO-178C Trace Evidence for Indian Safety-Critical Teams

Indian automotive, medical, aerospace, and defence teams need non-intrusive instruction trace for coverage evidence, crash forensics, and interrupt profiling. Here's why J-Trace PRO is the pragmatic answer.

15 Apr 2026 · 10 min read
Functional safety engineer reviewing ISO 26262 evidence package with SEGGER embOS-Safe on an Indian automotive Tier-1 desk
embOS SEGGER Automotive & Mobility

SEGGER embOS-Safe for Indian Automotive Tier-1 Teams: The Cheapest Credible Path to ISO 26262 ASIL D

Indian automotive Tier-1 suppliers building ASIL D components for domestic OEMs need a functional-safety-certified RTOS. SEGGER embOS-Safe is IEC 61508 SIL 3, ISO 26262 ASIL D, IEC 62304 Class C, and EN 50128 certified, and is materially cheaper than the alternatives. Here's the procurement and integration case.

14 Apr 2026 · 9 min read