Binho Supernova as a Saleae Logic I3C Protocol…

Binho Supernova as a Saleae Logic I3C Protocol Analyzer Plugin

Saleae Logic analyzers are on nearly every embedded engineer’s bench. Their combination of clean hardware, intuitive software, and extensive protocol decoder library has made them the default choice for digital bus debugging. But Saleae’s protocol decoder library, extensive as it is, does not include a native MIPI I3C decoder. As I3C adoption grows in sensor hubs, camera interfaces, and power management ICs, engineers need a way to see I3C traffic in their existing workflow.

The Binho Supernova addresses this gap directly. It functions as an I3C protocol analyzer that integrates with Saleae Logic 2 through Saleae’s High Level Analyzer (HLA) extension framework. The Supernova captures I3C bus traffic and presents decoded transactions within the Saleae Logic 2 interface, alongside any other protocol decoding the engineer is already running.

How the Integration Works

The Saleae Logic 2 software supports High Level Analyzers, Python-based plugins that process captured data and generate decoded protocol views. The Binho Supernova I3C analyzer plugin uses this framework to bring I3C decoding into the Saleae environment.

The workflow combines two tools:

Saleae Logic captures the raw I3C bus signals (SDA and SCL) as digital waveforms.
Binho Supernova HLA plugin decodes those waveforms into I3C protocol transactions, showing device addresses, read/write direction, data payloads, Common Command Codes (CCCs), in-band interrupts, and HDR-DDR transfers.

The decoded I3C transactions appear as annotations on the Saleae waveform view, in the same format as Saleae’s built-in I2C and SPI decoders. Engineers can scroll through the captured data, zoom into specific transactions, search for particular addresses or command codes, and correlate I3C activity with other bus traffic captured simultaneously.

What the Plugin Decodes

The Supernova’s I3C analyzer handles the full I3C protocol stack:

SDR (Single Data Rate) transactions. Standard I3C read and write operations at up to 12.5 MHz push-pull clock. Device addresses, data bytes, and T-bit handling are decoded and displayed.

CCC (Common Command Codes). Broadcast and directed CCCs are decoded with their command names, ENTDAA (Enter Dynamic Address Assignment), SETDASA (Set Dynamic Address from Static Address), GETPID (Get Provisioned ID), GETBCR (Get Bus Characteristics Register), and others. This is critical for debugging I3C bus initialization sequences where address assignment failures are a common issue.

In-Band Interrupts (IBI). When an I3C target device issues an IBI, the analyzer decodes the interrupt, identifies the interrupting device, and displays any mandatory data bytes. Debugging IBI behavior is one of the most challenging aspects of I3C development, seeing the IBI transactions decoded in the logic analyzer view makes the bus behavior visible.

HDR-DDR (High Data Rate, Double Data Rate). For I3C buses running in HDR-DDR mode, the analyzer decodes the higher-speed transactions that carry bulk data between controller and target devices.

Dynamic Address Assignment. The ENTDAA sequence, where the I3C controller discovers targets and assigns dynamic addresses, is decoded step by step, showing each target’s Provisioned ID, BCR, DCR, and assigned address. This visibility is essential when debugging multi-device I3C buses where address assignment does not complete as expected.

Why This Matters for I3C Adoption

I3C is a protocol where visibility into bus behavior is essential for successful development. Unlike I2C, where bus transactions are relatively simple and failure modes are well understood, I3C introduces dynamic addressing, in-band interrupts, multiple speed modes, and controller-target negotiation that create more complex failure scenarios.

Without protocol-level visibility, debugging an I3C bus that is not initializing correctly or dropping transactions requires guesswork. With the Supernova’s Saleae integration, engineers can see exactly what is happening on the bus, which CCCs are being sent, whether targets are responding to address assignment, whether IBIs are being acknowledged, and whether data transfers are completing correctly.

For design teams in Bengaluru and Hyderabad working on next-generation sensor platforms and mobile devices that use I3C, this visibility accelerates the development cycle by turning opaque bus failures into visible, diagnosable events.

Complementary to Supernova’s Native Capabilities

The Saleae plugin is complementary to the Supernova’s native I3C exerciser capabilities. The Supernova itself can generate I3C traffic, acting as an I3C controller to send transactions, assign addresses, and exercise target devices. The Saleae integration adds passive monitoring: capturing and decoding I3C traffic generated by other controllers on the bus.

This combination gives engineers two perspectives:

Active exercising with the Supernova driving the bus (through Mission Control or Python SDK)
Passive analysis with the Supernova decoding traffic captured by the Saleae Logic

Together, they cover the full I3C development workflow from initial device bring-up through system integration and debug.

Why Buy from GSAS

GSAS Micro Systems is the authorized Binho engineering partner in India. We provide the Supernova with INR invoicing and local support, including guidance on setting up the Saleae Logic integration. Our applications engineers in Bengaluru, Hyderabad, Chennai, Pune, Mumbai, and Delhi NCR can assist with I3C bus architecture review, Supernova configuration, and integration into existing debug workflows. Contact us for evaluation units or a technical consultation.